> Markdown version of [/jobs/ext/1766610-rtl-design-engineer](https://www.wearedevelopers.com/jobs/ext/1766610-rtl-design-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # RTL Design Engineer - **Company:** Mercor, Inc. - **Location:** United States (Remote available) - **Experience:** Experienced - **Contract:** Permanent contract - **Skills:** Software Debugging, Logic Synthesis of Circuits, Electronic Design Automation, Formal Verification, PCI Express, Static Timing Analysis, SystemVerilog, Verilog, System Availability, Large Language Models - **Published:** July 11, 2026 - **Apply:** https://find.jobs/jobs-near-me/apply/ats-redirect/?id=2875317578-2 ## About the Role 3-10 years of experience in digital RTL design - Strong proficiency in Verilog / SystemVerilog - Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols - Experience with ASIC design flows: lint, synthesis, timing analysis, CDC, DFT-aware design - Familiarity with common EDA tools for simulation, waveform debug, lint, CDC, synthesis, timing analysis - Familiarity with leveraging LLM-based tools to accelerate chip design, RTL development, debug, documentation, or verification workflows - Ability to write clear design documentation and communicate technical tradeoffs - Experience debugging RTL issues using simulation logs and waveform viewers - Strong collaboration skills across architecture, verification, and implementation teams Preferred - AMBA protocols (AXI, AHB, APB) - Background in one or more of: CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect, low-power design - Exposure to formal verification or SV/UVM-based design verification Track 2: Design Verification Engineer Qualifications - 3-10 years of experience in design verification - Strong proficiency in SystemVerilog and UVM - Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols - Experience developing reusable verification components and testbench infrastructure - Constrained-random verification, functional coverage, assertions (SVA), coverage closure - Familiarity with EDA tools for simulation, waveform debug, coverage analysis, formal verification, regression management - Familiarity with LLM-based tools to accelerate verification, debug, test generation, documentation, or coverage analysis - Ability to write clear verification plans, debug reports, and technical documentation Preferred - AMBA protocols (AXI, AHB, APB) - Background in one or more of: CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect, low-power verification - Reusable verification IP, scoreboards, reference models, coverage-driven regression flows Logistics - Location: Remote, USA and Canada only - Commitment: Full-time preferred; high availability required (40 hours) ## Description We are sourcing senior digital chip design and verification engineers to support an AI evaluation program focused on frontier silicon / chip-design workflows. We are targeting the next couple of months and will prioritize truly strong contributors who can commit meaningful time. ## Related Videos - [When testing just doesn’t cut it](https://www.wearedevelopers.com/videos/720-when-testing-just-doesn-t-cut-it) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [You don't need to write the code. You need to become a verification architect and prove it's correct](https://www.wearedevelopers.com/videos/100023-you-don-t-need-to-write-the-code-you-need-to-become-a-verification-architect-and-prove-it-s-correct) ## Related Articles - [Fully Remote Software Engineer Jobs](https://www.wearedevelopers.com/magazine/447-fully-remote-software-engineer-jobs) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [Find a Developer Job: 12 Best Job Sites For Developers](https://www.wearedevelopers.com/magazine/165-find-a-developer-job-12-best-job-sites-for-developers) - [Where To Find Software Engineering Jobs](https://www.wearedevelopers.com/magazine/396-where-to-find-software-engineering-jobs)