> Markdown version of [/jobs/ext/1781772-asic-fpga-verification-engineer-experienced-lead-or-senior](https://www.wearedevelopers.com/jobs/ext/1781772-asic-fpga-verification-engineer-experienced-lead-or-senior). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # ASIC/FPGA Verification Engineer (Experienced, Lead, or Senior) - **Company:** Boeing Company - **Location:** El Segundo, CA, United States - **Experience:** Experienced - **Salary:** $119,850.0 - $162,150.0 - **Contract:** Contract - **Skills:** Systems Engineering, Code Coverage, Computer Engineering, Software Debugging, Perl (Programming Language), Emulators, Ethernet, Field-Programmable Gate Array (FPGA), Revision Control Systems, Python (Programming Language), Linux System Administration, Object-Oriented Software Development, PCI Express, Regression Testing, Software Requirements Analysis, Subversion, SystemVerilog, Scripting, Application Specific Integrated Circuits, Git, Information Technology - **Published:** July 8, 2026 - **Apply:** https://dejobs.org/x/x/1D9397016384403CBF4CA5E4C6580FCE/job/ ## About the Role * Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement * 5+ years of proven experience in ASIC/FPGA verification processes * Familiarity with defining the architectural framework for ASIC/FPGA verification using SystemVerilog/UVM, including the delivery and release of production designs * Proficiency in hardware verification languages, particularly SystemVerilog and SystemVerilog Assertions * Demonstrated experience in implementing test plans effectively * Solid understanding of Object-Oriented Programming principles, such as Inheritance and Polymorphism * Capability to design self-checking and reusable testbenches from the ground up * Experience in developing Functional Coverage Models and achieving Code Coverage closure * Capable of collaborating with design and system engineering to establish accurate and verifiable ASIC/FPGA level specifications * Familiarity with waveform debug tools * Revision Control Systems: svn, cvs, git * Proficiency in Linux Environments, * Lead, Level 4 : 10+ years of related work experience or an equivalent combination of education and experience * Senior, Level 5 : 15+ years of related work experience or an equivalent combination of education and experience * Master's Degree in EE, Computer Engineering/Science, or related field, or equivalent experience * Experience with hardware-based integration and test of ASIC/FPGA designs * Experience with hardware emulators, especially Palladium * Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet) * Proficient in scripting languages: Make, Perl, Python, etc. * Familiarity with space-based design techniques and radiation mitigation * Demonstrated history of 1st pass success with ASIC designs Conflict of Interest: Successful candidate for this job must satisfy the Company's Conflict of Interest (COI) assessment process. Typical Education/Experience: Experienced, Level 3: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard. Lead, Level 4: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 9 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard. Senior, Level 5: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience or an equivalent combination of technical education and experience (e.g. PhD+9 years' related work experience, Master+12 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard., Bachelor's Degree or Equivalent Required, This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret Clearance Post-Start is required. ## Description * Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog. * Develop self-checking and reusable test benches from the ground up, employing Object-Oriented Programming principles such as Inheritance and Polymorphism, while utilizing UVM to build drivers, monitors, predictors, and scoreboards. * Create Functional Coverage Models and conduct Code Coverage analysis to ensure thorough verification of designs during simulation. * Set up regression tests and collect coverage metrics to ensure comprehensive verification and track progress over time. * Assist in FPGA-based prototyping and validation based on program and system requirements and complexity. * Collaborate with cross-functional teams to ensure that verification strategies align with overall project goals and timelines. ## Related Videos - [When testing just doesn’t cut it](https://www.wearedevelopers.com/videos/720-when-testing-just-doesn-t-cut-it) - [Thinking Differently - How to Make Money from Cyber Attacks & Cheats](https://www.wearedevelopers.com/videos/745-thinking-differently-how-to-make-money-from-cyber-attacks-cheats) - [The Gashlycrumb Tinies of AI Networking You Must Know (or Languish!)](https://www.wearedevelopers.com/videos/2067-the-gashlycrumb-tinies-of-ai-networking-you-must-know-or-languish) - [How a Small Team Shrank a Microsoft Monorepo by 94%](https://www.wearedevelopers.com/videos/1236-how-a-small-team-shrank-a-microsoft-monorepo-by-94) - [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) ## Related Articles - [Where to Find Entry-Level Software Engineering Jobs](https://www.wearedevelopers.com/magazine/397-where-to-find-entry-level-software-engineering-jobs) - [What’s the Difference between a Junior, Mid, and Senior Developer?](https://www.wearedevelopers.com/magazine/238-what-s-the-difference-between-a-junior-mid-and-senior-developer) - [How Much FAANG Companies Actually Pay Software Engineers in 2025](https://www.wearedevelopers.com/magazine/230-how-much-faang-companies-actually-pay-software-engineers-in-2025) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers) - [Should senior developers refuse interview coding challenges?](https://www.wearedevelopers.com/magazine/29-should-senior-developers-refuse-interview-coding-challenges)