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# Sr Principal Electrical Engineer - ASIC/FPGA (Onsite)

- **Company:** RTX
- **Location:** Fort Wayne, IN, United States
- **Experience:** Expert
- **Salary:** $132,400.0 - $251,600.0
- **Contract:** Permanent contract
- **Skills:** C (Programming Language), C++ (Programming Language), Software Debugging, Digital Architecture, Digital Electronics, Perl (Programming Language), Field-Programmable Gate Array (FPGA), Python (Programming Language), Software Engineering, Static Timing Analysis, SystemVerilog, Systems Integration, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Scripting, Application Specific Integrated Circuits, ModelSim
- **Published:** July 3, 2026
- **Apply:** https://globalhr.wd5.myworkdayjobs.com/REC_RTX_Ext_Gateway/job/US-IN-FT-WAYNE-150A--1010-Production-Rd--BLDG-150A/Sr-Principal-Electrical-Engineer---ASIC-FPGA--Onsite-_01857063-1

## About the Role

The ability to obtain and maintain a U.S. government issued security clearance is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance, * Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 10 years prior relevant experience or an Advanced Degree in a related field and minimum 7 years of experience

 * The ability to obtain and maintain a U.S. government issued security clearance is required
 * U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance
 * Hands-on experience with RTL design, coding, and simulation using VHDL and/or Verilog
 * At least 5+ years experience with digital circuit architecture, resource optimization, timing analysis, and timing closure
 * At least 5+ experience developing and executing RTL verification testbenches using VHDL or SystemVerilog
 * Proficiency with ASIC and/or FPGA simulation, synthesis, and implementation tools (ModelSim, Synplify, Quartus, Vivado, or similar)
 * Proven ability to lead cross-functional engineering teams while managing project scope, schedules, budgets, and technical deliverables, * Experience with ASIC/FPGA lab validation and debug using standard lab equipment, along with familiarity with DFT, manufacturability, and production test concepts.
 * Proficiency with Unix/Linux environments, scripting or software development (C, C++, Python, Perl, or shell), and industry-standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado.
 * Strong written and verbal communication skills, with the ability to work independently and collaboratively in fast-paced, multidisciplinary engineering environments.

## Description

* Requirements capture, ASIC/FPGA digital architecture design, RTL development, timing analysis and closure, verification, and system integration
 * Drive continuous improvement by identifying and implementing new tools, methodologies, and best practices within the ASIC/FPGA design flow
 * Contribute to engineering estimates and technical planning efforts for new program pursuits
 * Plan and execute project-level work while ensuring alignment to schedule, cost, and performance objectives
 * Provide technical leadership for project design teams by defining work scope, coordinating activities, and reporting project status
 * Support cross-functional collaboration throughout the development lifecycle to ensure successful delivery of high-performance digital solutions


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