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# MTS Digital Engineering

- **Company:** Rambus Inc.
- **Location:** Morrisville, NC, United States (Remote available)
- **Experience:** Starter
- **Salary:** $58,000.0 - $108,000.0
- **Contract:** Permanent contract
- **Skills:** Very-Large-Scale Integration, Computer Engineering, Software Debugging, Desktop Publishing, Perl (Programming Language), Python (Programming Language), Machine Learning, Static Timing Analysis, SystemVerilog, Verilog, State Machines, Physical Design
- **Published:** May 17, 2026
- **Apply:** https://www.careerjet.com/jobad/us60a71fed247dd6356cb32102e0d1c72e

## About the Role

* BS in Electrical Engineering with 2-3 years experience, or MS in Electrical Engineering or Computer Engineering with 0-1 year of experience
 * Coursework: Digital Integrated Circuits, Advanced VLSI Systems, Advanced Computer Architecture, Embedded Systems, Design and Analysis of Algorithms, Fundamentals of Machine Learning
 * Background in Digital RTL design including standard LEC, CDC, Lint, DFT, BIST, STA tools
 * High aptitude with Verilog and SystemVerilog
 * Ability to document design techniques, test, and verification methodology.
 * Python/perl script development
 * Interface with debug, test, product, and reliability engineers for product qualification

## Description

As a New College Graduate Design Engineer, the full-time position candidate will be responsible for specifying, architecting, implementing, and simulating RTL components. The individual will work closely with specification developers, digital & analog designers, and physical design teams to realize efficient and highest performance designs. The position is for DDR5 and DDR6 enterprise-class memory interface products to grow the Memory Interface Chip Business Unit.
Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.
Responsibilities

 * Develop system Verilog RTL IP, logic, and state machines for next generation products
 * Perform block level design integration and block level simulations to qualify behavior
 * Document design implementation with descriptions and functional diagrams
 * Estimate and track power, performance, area (PPA) tradeoffs for RTL designs
 * Collaborate with design team members individually and in group meetings to track status and ensure design implementation achieves desired outcomes
 * Review and improve Static Timing Analysis (STA) results
 * Creating Verilog functional models to be used in simulations
 * Work closely with verification team to debug verification results
 * Support validation team during chip power-on and debug efforts
 * Perform design quality checks with CDC/RDC/LINT tools


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