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# Design Engineering Architect

- **Company:** Cadence Design Systems, Inc.
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Boolean Algebra, Microarchitecture, Software Debugging, Firmware, Formal Verification, Subsystems, SystemVerilog, Verilog, VHSIC Hardware Description Language (VHDL), Information Technology, Front End Software Development, Physical Design
- **Published:** July 25, 2026
- **Apply:** https://www.juju.com/job/00000000gk6mkx

## About the Role

*10+ years of Front End design and/or verification with a BS/MS Engineering or Computer Sciences

*Proven experience in leading and managing complex engineering projects

*Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration

*Expert in RTL design (Verilog), simulators debuggers

*Hands on Experience in Synthesis, SDC creation and support PD and STA teams.

*Experience in driving results in multi-disciplinary organization

Desirable:

A Self-motivated person with good communication and design management skills

Experience with Cadence front end toolset

We're doing work that matters. Help us solve what others can't.

We're doing work that matters. Help us solve what others can't.

## Description

Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.

Design & Microarchitecture:

Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.

RTL Development:

Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.

Verification & Signoff:

Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.

Collaboration:

Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.


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