> Markdown version of [/jobs/ext/1840730-principal-engineer-hardware-application-engineering-signal-integrity-power-integrity](https://www.wearedevelopers.com/jobs/ext/1840730-principal-engineer-hardware-application-engineering-signal-integrity-power-integrity). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Principal Engineer, Hardware Application Engineering - Signal Integrity & Power Integrity - **Company:** I8IS INC. - **Location:** Santa Clara, CA, United States - **Experience:** Expert - **Salary:** $199,800.0 - $266,400.0 - **Contract:** Permanent contract - **Skills:** Big Data, Computer Engineering, Ethernet, Hardware Design, Signal Integrity, AI Infrastructure, Hfss, Reliability of Systems, Computerised Systems, Pcb Layout, Ansys, Hardware Debugging - **Published:** July 31, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=6eb2ad27ea088adc ## About the Role The position is a highly visible individual contributor role requiring deep technical expertise, strong customer engagement skills, and the ability to influence engineering teams across multiple disciplines., Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or related discipline. 15+ years of experience in hardware design, development, and validation of high-speed networking or computing systems. 10+ years of specialized experience in signal integrity and power integrity for high-speed SerDes platforms. Strong expertise across the complete SI lifecycle: Channel modelling and budgeting PCB layout and stack-up definition Post-layout extraction and simulation Design optimization and troubleshooting Compliance testing and tuning Strong understanding of power integrity concepts including PDN modelling, impedance analysis, IR drop, and transient behaviour. Experience with SI/PI simulation tools such as Ansys HFSS/SIwave, Cadence Sigrity/Clarity/PowerSI, or equivalent. Hands-on experience with high-speed validation equipment: VNAs BERTs Real-time and sampling oscilloscopes TDR systems Jitter analysers Proven experience supporting customer-facing engineering engagements. Ability to communicate complex technical concepts to engineering teams and senior stakeholders., Experience with Ethernet switching platforms, networking ASICs, or AI infrastructure systems. Experience supporting large-scale data centre deployments. Background in customer enablement and reference platform development. Familiarity with ODM/CM design processes, qualification flows, and manufacturing requirements. Experience with SerDes tuning methodologies and correlation between simulation, lab results, and field data. Knowledge of chip-to-module, cable, connector, and high-speed interconnect ecosystems. Demonstrated ability to influence product roadmaps through technical insights. ## Description The organization is seeking a Principal Engineer specializing in Signal Integrity (SI) and Power Integrity (PI) to serve as a senior technical authority supporting high-performance networking and AI infrastructure platforms. This role will focus on ensuring customer systems built on advanced silicon solutions meet the highest standards for performance, reliability, and production readiness. The engineer will lead SI/PI activities across the complete product lifecycle, including architecture definition, simulation, validation, compliance testing, customer enablement, and production ramp., Serve as the senior SI/PI technical authority for customer platforms from early architecture through mass production. Define and maintain high-speed layout, routing, stack-up, and power delivery guidelines. Perform channel extraction, simulation, and design analysis for high-speed SerDes interfaces. Provide recommendations to improve signal margins, performance, and system reliability. Lead compliance testing and lab characterization, including BER/SER, eye diagrams, jitter, return loss, and crosstalk analysis. Provide SerDes tuning guidance based on simulation results, lab measurements, and system data. Perform power integrity analysis including PDN impedance, IR drop, transient response, decoupling effectiveness, and voltage droop. Review customer and partner designs and provide SI/PI recommendations. Collaborate with silicon, packaging, hardware, software, and operations teams to improve platform solutions. Support reference platform development and validate SI/PI performance for new products. Lead hands-on hardware debugging using advanced laboratory equipment such as VNAs, BERTs, oscilloscopes, TDR systems, and jitter measurement tools. Develop technical training materials and deliver SI/PI best-practice sessions for customers and internal engineering teams. Provide technical leadership for current and future high-speed SerDes technologies. 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