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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # DMTS Digital Design Engineer / Chip Lead - **Company:** Micron Technology, Inc. - **Location:** Boise, ID, United States - **Experience:** Expert - **Salary:** $206,000.0 - **Contract:** Permanent contract - **Skills:** Application Integration Architecture, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Network Interface Controllers, S Interface, Static Timing Analysis, SystemVerilog, Application Specific Integrated Circuits, Physical Design - **Published:** July 31, 2026 - **Apply:** https://www.juju.com/job/00000000gkpg3a ## About the Role + BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field + 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or senior designer role + Expert-level proficiency in SystemVerilog RTL design and coding best practices + Strong experience with logic synthesis tools (Synopsys Design Compiler or Cadence Genus) and static timing analysis (PrimeTime or Tempus) + Proficiency with industry-standard RTL simulation and debug tools (VCS, Xcelium, or equivalent; Verdi or DVE for waveform debug) + Solid understanding of CDC analysis methodologies and tools (SpyGlass, JasperGold CDC, or equivalent) + Demonstrated experience integrating hard and soft IP blocks in a mixed-signal or PHY-adjacent chip environment + Ability to work effectively as a technical lead on a small team - comfortable making decisions with incomplete information and owning the outcomes + Strong written communication skills - this role produces specifications, not just code Preferred Qualifications + Experience with high-speed PHY architectures (SerDes, DDR, or equivalent analog I/O structures) + Familiarity with I2C management bus architecture, Eye Monitor control logic, or PRBS-based error counting implementations + Experience with DFT strategy definition including scan insertion, ATPG planning, and boundary scan for high-speed I/O + Familiarity with OTP/fuse-based trim and calibration architectures for PHY analog parameters + Prior experience in a small team or startup-like environment where role boundaries are defined by need rather than org chart ## Description Micron's Interface Pathfinding team operates at the leading edge of that mission - driving performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3-5 year technology horizon. As the Digital Design Engineer / Chip Lead, you will be the technical anchor of a small, senior team spanning analog design, layout, silicon characterization, physical design, and verification - united around the goal of carrying high-speed interface innovations from architecture to tape-out. This is a full-ownership role. You will define top-level chip architecture, author and maintain synthesizable RTL for all soft IP control blocks, own timing constraints and clock domain crossing strategy, drive synthesis and tape-out sign-off, and produce the design documentation that serves as the authoritative reference for the team. The program integrates a fully custom analog PHY alongside digital control functions - providing a technically rich chip-lead scope that spans hard macro integration, third-party IP management, and original RTL design. This is a foundational hire for a growing program. Strong execution early is expected to lead to follow-on projects of increasing scope, team size, and design complexity. Responsibilities + **Chip Architecture & Integration:** Define top-level chip architecture, partition responsibilities across hard and soft IP blocks, and own the integration of hard macros alongside third-party soft IP. + **RTL Design:** Author, review, and maintain synthesizable RTL (SystemVerilog) for all soft IP control blocks, CSR/register file, clocking control logic, and top-level integration. + **Timing Closure Leadership:** Develop and own chip-level timing constraints (SDC), define clock domain crossing strategy, and provide timing budgets per block to the Physical Design engineer. + **Synthesis:** Drive logic synthesis (DC / Genus) and guide optimization for PPA targets across all design blocks. + **IP Management:** Define interfaces between PHY hard macro, third-party soft IP, and internally designed blocks; manage IP integration agreements and vendor coordination. + **Tape-Out Ownership:** Own and drive the tape-out checklist sign-off process, coordinating across Physical Design, Verification, and analog team members to achieve clean handoff to the foundry. + **Design Documentation:** Author architecture specifications, block-level design specifications, and interface control documents that serve as the authoritative reference for the team. + **Follow-On Roadmap:** Capture design decisions, lessons learned, and architectural rationale to accelerate follow-on chip development. ## Related Videos - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Building a fully automated escape room](https://www.wearedevelopers.com/videos/735-building-a-fully-automated-escape-room) - [Designing AI-first products: When the interface is no longer the product](https://www.wearedevelopers.com/videos/2062-designing-ai-first-products-when-the-interface-is-no-longer-the-product) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [Designing for Every Direction: Logical CSS for Global, Adaptive, and Effortlessly Reversible UIs](https://www.wearedevelopers.com/videos/2026-designing-for-every-direction-logical-css-for-global-adaptive-and-effortlessly-reversible-uis) - [AI-Driven Interfaces: Designing the New Grammar of Interaction](https://www.wearedevelopers.com/videos/2014-ai-driven-interfaces-designing-the-new-grammar-of-interaction) ## Related Articles - [Should Tech Managers Be Developers First? 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