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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Digital Front-End Design Engineer - **Company:** Imec - **Location:** Leuven, Belgium - **Experience:** Starter - **Contract:** Permanent contract - **Skills:** Code Coverage, Computer Engineering, Desktop Publishing, Electronic Design Automation, Python (Programming Language), SystemVerilog, Tcl (Programming Language), Scripting, Application Specific Integrated Circuits, Information Technology, Front End Software Development, Physical Design - **Published:** August 1, 2026 - **Apply:** https://imec.csod.com/ux/ats/careersite/29/requisition/8974/application#1 ## About the Role Research Field Computer science Education Level Master Degree or equivalent, You are an ASIC design professional with a strong interest in front-end methodologies and a passion for delivering high-quality silicon. You bring: * 0-2 years of experience in ASIC front-end design, including RTL-to-Netlist flow. A master's degree in a related field (electrical or computer engineering) is required for candidates with no industry experience. * Expertise in synthesis, DFT, LEC, ATPG, and test coverage improvement. * Hands-on experience with Cadence (preferred) (Genus, Modus, Conformal, Xcelium, etc.) and/or Synopsys toolsets (DC, FC, TestMAX, SpyGlass, etc.). * Familiarity with Tessent tools for DFT and ATPG. * Understanding of and strong interest in digital design principles, timing closure, and test strategies. * Proficiency in Verilog/SystemVerilog and scripting languages (Tcl, Python, etc.). * Strong problem-solving skills and ability to work in cross-functional teams. * Eagerness to learn and improve. * Excellent communication skills and attention to detail. Languages ENGLISH ## Description Digital Front-End Design Engineer - Drive the complete RTL-to-GDS flow and shape next-generation silicon solutions., As a Digital Front-End Design Engineer, you are responsible for all design tasks in the RTL-to-GDS flow, ensuring high-quality and efficient implementation of complex ASIC designs. You work within a highly skilled Front-End (FE) team that provides design services to both internal IMEC research groups and external customers worldwide. The team consists of 10 members with diverse experience levels, offering a collaborative environment for knowledge sharing and technical growth. * Perform RTL synthesis and optimize timing, area, and power. * Execute DFT (Design-for-Test) insertion using industry-standard tools. * Conduct Logical Equivalence Checking (LEC) to validate design integrity. * Generate and validate ATPG (Automatic Test Pattern Generation) patterns. * Improve test coverage through advanced methodologies. * Run pre-layout and post-layout test pattern simulations to ensure robustness. * Collaborate closely with physical design teams for seamless RTL-to-GDS integration. * Utilize Cadence/Synopsys EDA tools for synthesis, DFT insertion, and ATPG. * Apply Tessent (Siemens) tools for DFT insertion and ATPG in specific projects. * Troubleshoot and resolve design issues across the front-end flow. * Document design processes and contribute to continuous improvement initiatives. * Engage with internal and external stakeholders to deliver high-quality design services. ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Mutation Testing and Fuzzing in C#](https://www.wearedevelopers.com/videos/703-mutation-testing-and-fuzzing-in-c) - [JavaScript? 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