> Markdown version of [/jobs/ext/1881143-senior-principal-engineer-hardware-chip-lead-connectivity-bu](https://www.wearedevelopers.com/jobs/ext/1881143-senior-principal-engineer-hardware-chip-lead-connectivity-bu). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior Principal Engineer - Hardware Chip Lead, Connectivity BU - **Company:** Marvell - **Location:** Santa Clara, CA, United States - **Experience:** Expert - **Salary:** $182,360.0 - $273,200.0 - **Contract:** Internship / Graduate position - **Skills:** Adobe InDesign, Artificial Intelligence, Computer Engineering, Microarchitecture, Software Debugging, Logic Synthesis of Circuits, Firmware, Hardware Design, Release Management, System on a Chip, Application Specific Integrated Circuits, Bots, Physical Design, GPT - **Published:** August 1, 2026 - **Apply:** https://diversityjobs.com/main/sendform/8/8/28176/1/17767996?backUrl=%2Fcareer%2F17767996%2FSenior-Principal-Engineer-Hardware-Chip-Lead-Connectivity-Bu-California-Santa-Clara ## About the Role * Bachelor's degree in Electrical Engineering, Computer Engineering, or related field and 15+ years of related professional experience * OR Master's degree in Electrical Engineering, Computer Engineering, or related field with 10-12 years of experience * OR PhD in Electrical Engineering, Computer Engineering, or related field with 8-10 years of experience, * Proven track record as a chip lead or equivalent technical owner on complex SoC/ASIC programs, from architecture through tape-out and post-silicon productization * Deep expertise in high-speed mixed-signal SoC design, including SerDes (100G+/lane), DSP datapath, analog/digital integration, and advanced CMOS process nodes (5nm, 3nm) * Strong understanding of the full ASIC design flow: micro-architecture, RTL, synthesis, DFT, physical design, STA, timing closure, and tape-out * Experience leading and coordinating cross-functional hardware teams across analog, digital, DV, DFT, PD, firmware, validation, and test engineering disciplines * Demonstrated ability to drive silicon bring-up, debug, and validation across multi-site global teams * Experience with ATE test program development, silicon characterization, qualification (HTOL, ESD, LU), and production release * Excellent communication, interpersonal, and presentation skills; ability to represent hardware engineering to BU leadership and cross-functional stakeholders * Highly motivated, self-driven, and able to manage ambiguity in a fast-paced, multi-program environment Preferred Skills * Familiarity with optical DSP, coherent or direct-detect transceiver architectures, or high-speed retimer products * Experience with eAVS (Adaptive Voltage Scaling) or similar power optimization subsystems * Knowledge of SiPho (Silicon Photonics) integration and module-level validation * Experience working in a multi-site, globally distributed engineering organization ## Description * Serve as the primary hardware technical owner for an ODSP chip program, responsible for tracking and driving progress across all hardware design phases from POR (Plan of Record) through MPR (Mass Production) * Finalize the Product Requirements Document (PRD) and bring-up requirements in collaboration with architecture, marketing, and applications engineering teams * Represent hardware engineering at all key program milestones: Pre-PA, PA, PSM, POR, Design Reviews, Tape-Out, and MPR * Coordinate and align cross-functional teams including analog design, digital design, DV, DFT, physical design, STA, firmware, validation, ATE/test engineering, product engineering, and quality * Manage and communicate program status, risks, and mitigation plans to BU engineering leadership on a regular cadence Technical Leadership * Provide technical leadership for the full chip design, independently proposing and defining high-level technical solutions across the hardware stack * Set technical direction and drive resolution of complex, cross-disciplinary design challenges spanning analog/digital integration, high-speed SerDes, DSP datapath, and SoC architecture * Proactively identify technical risks early in the design cycle and drive mitigation strategies across functional teams * Take an active role in setting and prioritizing BU milestones and objectives; participate in architecture and design reviews at the chip and block level * Drive continuous improvement in design methodology, flows, and quality across the ODSP hardware organization Design & Execution * Lead end-to-end chip design execution across advanced CMOS nodes (TSMC 2nm/3nm/5nm), including architecture, RTL, physical design, DFT, timing closure, and tape-out * Own the chip bring-up plan and execution, coordinating multi-site teams across global locations; drive Phase 0, Phase 1, and Phase 2 bring-up activities through to silicon validation * Oversee silicon validation, PVT characterization, ATE test program development, qualification (ESD, LU, HTOL), and production release * Drive resolution of post-silicon issues, coordinating debug across analog, digital, firmware, and validation teams * Ensure all hardware deliverables - including PRD, design documentation, and bring-up requirements - are complete and on schedule Mentorship & Knowledge Sharing * Mentor and develop engineers across the ODSP hardware organization; invest in building technical depth and breadth within the team * Foster a culture of knowledge sharing, technical rigor, and continuous learning * Coach and develop engineering talent; provide guidance and feedback to support career growth at all levels, Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. ## Related Videos - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [ Evaluating AI models for code comprehension](https://www.wearedevelopers.com/videos/1462-evaluating-ai-models-for-code-comprehension) - [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine) - [Command the Bots: Mastering robots.txt for Generative AI and Search Marketing](https://www.wearedevelopers.com/videos/1165-command-the-bots-mastering-robots-txt-for-generative-ai-and-search-marketing) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [Speak, Code, Deploy: Transforming Developer Experience with Voice Commands](https://www.wearedevelopers.com/videos/1159-speak-code-deploy-transforming-developer-experience-with-voice-commands) ## Related Articles - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers) - [How software is steering vehicle technology](https://www.wearedevelopers.com/magazine/515-how-software-is-steering-vehicle-technology) - [What’s the Difference between a Junior, Mid, and Senior Developer?](https://www.wearedevelopers.com/magazine/238-what-s-the-difference-between-a-junior-mid-and-senior-developer) - [From developer to manager – what does it take to become an engineering manager?](https://www.wearedevelopers.com/magazine/42-from-developer-to-manager-what-does-it-take-to-become-an-engineering-manager) - [Should Tech Managers Be Developers First? Pros and Cons](https://www.wearedevelopers.com/magazine/327-should-tech-managers-be-developers-first-pros-and-cons) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline)