> Markdown version of [/jobs/ext/1882022-cpu-performance-architect](https://www.wearedevelopers.com/jobs/ext/1882022-cpu-performance-architect). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # CPU Performance Architect - **Company:** Intel Corporation - **Location:** Folsom, CA, United States - **Experience:** Expert - **Salary:** $190,610.0 - **Contract:** Permanent contract - **Skills:** C++ (Programming Language), Software Debugging, Microprocessors, Interoperability, Object-Oriented Software Development, Performance Tuning, Reduced Instruction Set Computing, Subsystems, Scripting, Standard Template Library (STL), Decoding - **Published:** August 2, 2026 - **Apply:** https://www.careerbuilder.com/job-details/senior-cpu-performance-architect-folsom-ca--ef7e1bb6-9f5c-4659-81de-cb3dc669306d ## About the Role * Candidate must have experience in designing high performance CPUs and should be an expert in at-least one or multiple domains across the CPU (Branch Prediction, Fetch/Decode, Rename/Allocation, Reservation Stations/Execution, Memory Subsystem or Prefetchers and its interactions with Uncore). * Experience in debugging microarchitecture and simulation issues. * Strong background in microarchitecture/RTL/logic development. * Proven ability to resolve complex problems, applying analytical and technical skills effectively., * The candidate must have a Master's Degree with at 10+ years of experience or a PhD (with dissertation within a general CPU performance domain) with 6+ years of experience working within a high performance, high frequency ARM or x86 CPU performance team. * Candidate must have at 8+ years of continuous work within cycle accurate C++ CPU performance simulators Preferred Qualifications * Background in CPU microarchitecture and experience modeling features in a cycle accurate performance simulator. * Experience in microarchitecture exploration and identifying new features which provide IPC across the CPU. * Experience with CPU performance related activities from inception to real silicon (pathfinding, definition, correlation with RTL and Post-Si performance debug and tuning) * Experience with performance scenarios/use cases and KPI/workloads * Advanced skills with Object Oriented Programming (C++/STL) and scripting languages * Ability to write assembly and craft tests to evaluate and debug microarchitectural features * Ability to read/debug performance issues in RTL, ARM (Advanced RISC Machine), Analysis Skills, Architectural Design, C++ Programming Language, C++ Standard Template Library (STL), CPU (Central Processing Unit), Computer Architecture, Cross-Functional, Debugging Skills, Design Verification, Feasibility Analysis, Intel Product Family, Interoperability Requirements, Leadership, Low Power, Market Segmentation, Memory Subsystem, Object Oriented Programming (OOP), Performance Metrics, Performance Modeling, Performance Tuning/Optimization, Problem Solving Skills, Product Lifecycle, Product Positioning, Scripting (Scripting Languages), Simulation, Testing, Trade-Off Analysis, Use Cases, Validation Testing, Verification Engineering, Writing Skills, x86 Processors ## Description * Develops and drives end-to-end CPU microarchitecture specifications for highly optimized, modular, and scalable CPU based on hardware features, requirements, and interoperability of hardware and software throughout the product life cycle. * Evaluates feasibility tradeoffs, explores, and defines new approaches and novel microarchitectures for CPU. * Models CPU performance and power characteristics and analyzes the bottlenecks of current performance features on workloads that reflect CPU future usage. * Collaborates with architects, design, verification, and validation engineers during the execution of the project. * Delivers definition of new microarchitecture and finds mitigations for issues that arise during feature implementation to improve the overall design of CPU and overcome bottlenecks and constraints. * Participates in the debug and fixing of performance miscorrelation between RTL and\or silicon results against the performance model., This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. 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