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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # FPGA Engineer - **Company:** Xona Space Systems - **Location:** Burlingame, CA, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Software Debugging, Emulators, Field-Programmable Gate Array (FPGA), Global Positioning Systems (GPS), Hardware Design, Internet Protocol, Signal Processing, Static Timing Analysis, Systems Architecture, System Testing, Systems Integration, Hardware Testing, System-level Testing, SC Clearance, GNSS - **Published:** July 31, 2026 - **Apply:** https://www.careerbuilder.com/job-details/sr-fpga-engineer-burlingame-ca--2b1772c2-e36a-42c2-a8a2-389f72afab7a ## About the Role * PhD or MS/BS in EE/CE or related field, 7+ years of FPGA and DSP implementation experience. * Demonstrated ownership of complex FPGA signal-processing systems from architecture to hardware validation. * Deep expertise in fixed-point DSP implementation, pipelining, and resource optimization. * Strong experience with high-speed interfaces and complex FPGA subsystems. * Expert proficiency with FPGA toolchains, static timing analysis, and on-chip debugging. Preferred Qualifications: * Experience with satellite communications, esp. with GNSS receivers and in spread-spectrum systems. * Familiarity with processing of satellite-related measurements (code/carrier/Doppler/CN0, PRs, DRs). * Experience supporting HIL and over-the-air validation environments. Key Competencies: * Strong DSP foundation with practical FPGA implementation expertise. * Execution-focused mindset with emphasis on timing closure and hardware validation. * Clear technical communication and documentation. * Ability to collaborate across systems, RF, software, and navigation teams to deliver flight-ready FPGA solutions. For U.S. Roles: To comply with U.S. Government space technology export regulations, applicant must be a U.S. citizen, lawful permanent resident of the United States (i.e. Green Card holder), or other protected individual as defined by 8 U.S.C. 1324b(a)(3). For U.K. Roles: To comply with U.K. regulations, this role requires Baseline Personnel Security Standard (BPSS) checks, and successful candidates must be eligible to obtain UK Security Clearance (SC). For Canada Roles: Successful candidates must obtain and hold a security clearance at the reliability status level, and pass security assessment for the Canadian Controlled Goods Program (CGP) and ITAR. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status. Skills: Architectural Services, Best Practices, Budgeting, Communication Skills, Cross-Functional, FPGA, GPS (Global Positioning System), Government, Hardware Architecture, Hardware Design, Hardware-Software Integration, IP (Internet Protocol), Intellectual Property Analysis, Mathematics, Performance Management, Program Control, Radio Frequency, Receivers, Regulations, Risk Management, Satellite Communications, Security Analysis, Security Clearance, Signal Processing, Simulation, System Architecture, System Test, Team Player, Technical Leadership, Technical Writing, Timing Verification, UK Security Clearances, United States Citizen ## Description We're seeking a Senior FPGA Engineer to lead the architectural specification and design of next-generation LEO PNT satellite systems. You will own the FPGA signal-processing pipeline from concept through flight-ready hardware, making critical trade-offs between mathematical idealization and physical hardware constraints. What you'll Do * FPGA Architecture Ownership: Define and specify hardware architecture for high-dynamic acquisition, tracking, data decoding, and measurement processing pipelines. * DSP/FPGA Implementation: Lead fixed-point design, resource budgeting, and pipeline optimization to achieve performance and latency targets. * Technical Leadership: Establish RTL best practices and guide junior engineers through complex design cycles and hardware validation phases. * Cross-Functional Integration & HW/SW Partitioning: Define and optimize HW/SW partitioning in collaboration with SW teams; ensure efficient SW interfaces, seamless integration, robust system-level testing, and preservation of performance margins. * Performance & Risk Management: Drive timing closure, power optimization, and system-level performance verification; resolve complex cross-domain issues. * Vendor & IP Integration: Evaluate and integrate third-party IP cores, define acceptance criteria and compliance testing. * Verification Strategy: Establish robust verification frameworks, including simulation, emulation, and hardware validation. ## Related Videos - [Thinking Differently - How to Make Money from Cyber Attacks & Cheats](https://www.wearedevelopers.com/videos/745-thinking-differently-how-to-make-money-from-cyber-attacks-cheats) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [WeAreDevelopers LIVE – Web Scraping, Agents, Actors and more](https://www.wearedevelopers.com/videos/1764-wearedevelopers-live-web-scraping-agents-actors-and-more) - [Your next 10x engineer isn't in your city. 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