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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Systems and Test Integration Engineer - FPGA Integration & Verification - **Company:** General Dynamics Mission Systems, Inc. - **Location:** Scottsdale, AZ, United States - **Salary:** $100,767.0 - **Contract:** Permanent contract - **Skills:** Testing (Software), Board Bringup, Systems Engineering, Ubuntu (Operating System), Command-Line Interface, Code Review, Computer Networks, Continuous Integration, Software Debugging, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Hardware Design, Integrated Development Environments, Subnetting, Joint Test Action (IEEE Standards), Python (Programming Language), Linux System Administration, Unix Shell, Routing, Scrum Methodology, Red Hat Enterprise Linux, Release Management, SystemVerilog, Systems Integration, Tcl (Programming Language), VHSIC Hardware Description Language (VHDL), Vivado, Scripting, Hardware Testing, Git, Gitlab-ci, Git Flow, Integration Tests, Software Version Control - **Published:** August 4, 2026 - **Apply:** https://www.techcareers.com/job.asp?id=3341147304&tx=YT808CYV&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54 ## About the Role Bachelor's degree in Systems Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 2 years of relevant experience; or Master's degree, plus 6 months of relevant experience., Department of Defense TS/SCI security clearance is preferred at time of hire. Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required., * 3+ years of experience in FPGA design, integration, and hardware bring-up, spanning microarchitecture definition through hardware integration * Proficiency in SystemVerilog and/or VHDL for RTL design * Comfortable writing designer-level testbenches to stimulate and validate your own submodules in simulation before hardware * Ability to work at the systems level: understanding how the surrounding system drives test FPGA requirements and how the test FPGA fits into the larger test-and-integration picture * Hands-on experience designing and integrating FPGA interfaces such as Ethernet, JESD204B/C, SPI, etc. * Proficiency in synchronous and asynchronous design principles, timing closure, and constraint generation * Experience with FPGA vendor toolchains (Xilinx/AMD Vivado, Lattice Diamond/Radiant, or equivalent) * Hands-on experience integrating FPGA interfaces in a lab environment (JTAG, oscilloscopes, protocol analyzers, debugging on real hardware) * Proficiency in scripting languages such as Linux shell scripts, Python, and Tcl * Experience with Git-based version control workflows (branching strategies, merge requests, code review) * Experience working in Linux environments (RHEL, Ubuntu); comfortable at the command line * Familiarity with CI/CD platforms (GitLab CI or equivalent) for FPGA build and release automation * Experience with computer networking (Ethernet configuration, subnets, routing) * Familiarity with agile/scrum workflows and sprint-based delivery * Experience deriving test FPGA requirements from system-level needs: working with hardware, systems, and test engineers to define what a test FPGA has to do, not just implementing a fully-architected design ## Description As a Systems and Test Integration Engineer - FPGA Integration & Verification, on the GDMS TIDES team, you will do two related kinds of FPGA work that support spacecraft payload development. You will design FPGAs from architecture through implementation for the shared test infrastructure. These are FPGAs that handle interface bridging between the test equipment and the unit-under-test, real-time functions like packet timestamping and precision command scheduling, and other test-support work. You will also bring up FPGA interfaces on real hardware, maturing the development platform and enabling test software infrastructure to be built. This is FPGA engineering for the Hardware Development Environment (HDE), a shared engineering platform that all spacecraft payload programs at GDMS build on. In this role you will own FPGA features end to end, from microarchitecture through lab bring-up, and grow toward independently architecting test FPGAs. Your work directly enables faster hardware bring-up, more reliable integration testing, and a smoother path from development to design verification to flight readiness. You will contribute to FPGA architecture decisions, write RTL, establish interface communications in the lab, and help shape how the HDE evolves, all in a mission-focused environment., * Design FPGAs for the shared test infrastructure, including interface translation between the unit under test and the test system, and real-time functions like packet timestamping and precision command scheduling * Integrate and debug FPGA communication interfaces on real hardware * Build and maintain CI/CD stages that produce FPGA artifacts to be used by the shared development environment (Python packages, versioned images, published binaries) * Collaborate with the test software and test hardware groups to define interfaces, coordinate integration, and align on platform capabilities * Contribute to the platform's evolution across versions as the HDE grows toward full flight-representative capability * Debug firmware issues using lab instrumentation, waveform capture, and structured investigation * Document FPGA designs, bring-up procedures, and integration approaches ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Creating a routing app with Google Maps API from scratch](https://www.wearedevelopers.com/videos/831-creating-a-routing-app-with-google-maps-api-from-scratch) - [How a Small Team Shrank a Microsoft Monorepo by 94%](https://www.wearedevelopers.com/videos/1236-how-a-small-team-shrank-a-microsoft-monorepo-by-94) - [Remote Driving on Plant Grounds with State-of-the-Art Cloud Technologies](https://www.wearedevelopers.com/videos/251-remote-driving-on-plant-grounds-with-state-of-the-art-cloud-technologies) - [Security Pitfalls for Software Engineers](https://www.wearedevelopers.com/videos/726-security-pitfalls-for-software-engineers) - [A Technical Introduction to Bitcoin's 2nd Layer- The Lightning Network](https://www.wearedevelopers.com/videos/15-a-technical-introduction-to-bitcoin-s-2nd-layer-the-lightning-network) ## Related Articles - [Should senior developers refuse interview coding challenges?](https://www.wearedevelopers.com/magazine/29-should-senior-developers-refuse-interview-coding-challenges) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [How software is steering vehicle technology](https://www.wearedevelopers.com/magazine/515-how-software-is-steering-vehicle-technology) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Is Software Engineering Hard?](https://www.wearedevelopers.com/magazine/448-is-software-engineering-hard) - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers)