> Markdown version of [/jobs/ext/1933579-rtl-design-engineer](https://www.wearedevelopers.com/jobs/ext/1933579-rtl-design-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# RTL Design Engineer

- **Company:** Broadcom
- **Location:** Chandler, AZ, United States
- **Experience:** Expert
- **Salary:** $127,100.0 - $203,400.0
- **Contract:** Permanent contract
- **Skills:** Apple IOS, Software Debugging, Digital Architecture, Logic Synthesis of Circuits, Perl (Programming Language), Formal Verification, Python (Programming Language), Static Timing Analysis, SystemVerilog, Systems Integration, Tcl (Programming Language), Verilog, Scripting
- **Published:** August 5, 2026
- **Apply:** https://broadcom.wd1.myworkdayjobs.com/External_Career/job/USA-AZ-Chandler-North-Juniper-Drive/RTL-Design-Engineer_R025142-1

## About the Role

* MS +10 years of relevant industry experience.
 * Experience with digital implementation flow from RTL synthesis to timing closure.
 * Deep understanding of timing analysis with Primetime flow and generation of Liberty models.
 * Experience with Tessent tool for DFT insertion and verification
 * Proficient with Perl, Python and Tcl scripting.
 * Strong problem solving skills with attention to detail.
 * Must be self-motivated and able to work effectively across internal and external engineering teams.

Highly Desired Qualifications

 * Solid understanding of transistor-level circuit behavior.
 * Familiar with Cadence Schematic/Layout, SPICE/Spectre circuit simulation.
 * Experience with advanced FinFET process nodes , including features, technology limitations and PPA tradeoffs.

## Description

Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and verification of a broad range of analog mixed signal IP and IOs, including leading-edge AI programs on advanced nodes. Joining a world-class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development.

 * Define the digital architecture and verification strategies for complex AMS and IO subsytems
 * Design, synthesis, and verification of Verilog/SystemVerilog RTL.
 * Analysis, debug, and resolution of Lint and CDC issues in the design.
 * Design convergence to timing closure utilizing RTL optimization strategies.
 * Conduct formal verification of design with Synopsys Formality / Cadence Conformal.
 * Generate timing constraints for Synthesis and STA at the block-level and SoC top-level.
 * Drive comprehensive test plans to ensure quality of design.
 * Collaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration.
 * Create and maintain detailed specification, design, and verification documentation.


## Related Videos

- [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips)
- [JavaScript? No. Java Scripts! - Scripting with Java](https://www.wearedevelopers.com/videos/2094-javascript-no-java-scripts-scripting-with-java)
- [Xcode development redefAIned](https://www.wearedevelopers.com/videos/100195-xcode-development-redefained)
- [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right)
- [Intermediate Bitcoin Script](https://www.wearedevelopers.com/videos/25-intermediate-bitcoin-script)
- [Harnessing Apple Intelligence: Live Coding with Swift for iOS](https://www.wearedevelopers.com/videos/1515-harnessing-apple-intelligence-live-coding-with-swift-for-ios)

## Related Articles

- [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers)
- [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers)
- [The Best X (Twitter) Accounts for Developers](https://www.wearedevelopers.com/magazine/294-the-best-x-twitter-accounts-for-developers)
- [The Best Software Developer Blogs to Read](https://www.wearedevelopers.com/magazine/156-the-best-software-developer-blogs-to-read)
- [Dev Digest 139 - Soft and hard queries](https://www.wearedevelopers.com/magazine/487-dev-digest-139-soft-and-hard-queries)
- [Dev Digest 188: CfP time, the risks of NPM and IKEA algorithms](https://www.wearedevelopers.com/magazine/635-dev-digest-188-cfp-time-the-risks-of-npm-and-ikea-algorithms)