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# ASIC III - AMZ10291241

- **Company:** Amazon.com, Inc.
- **Location:** Sunnyvale, CA, United States
- **Experience:** Expert
- **Salary:** $236,558.0 - $247,600.0
- **Contract:** Permanent contract
- **Skills:** Memory Management, Perl (Programming Language), Formal Verification, Python (Programming Language), Static Timing Analysis, Subsystems, System on a Chip, Tcl (Programming Language), Application Specific Integrated Circuits, Information Technology, Physical Verification, Physical Design
- **Published:** August 6, 2026
- **Apply:** https://www.amazon.jobs/en/jobs/10492070/asic-iii-amz10291241

## About the Role

Master's degree or foreign equivalent degree in Computer Science, Engineering, or a related field and five years of experience in the job offered or a related occupation. Employer will accept a Bachelor's degree or foreign equivalent degree in Computer Science, Engineering, or a related field and seven years of progressive post-baccalaureate experience in the job offered or a related occupation as equivalent to the Master's degree and five years of experience. Must have five years of experience with the following skill(s): (1) experience with Static Timing Analysis (STA) including definition and development of signoff methodology and corresponding implementation solutions; (2) creating physical design flow automation scripts using Tcl, Perl, or Python; (3) developing physical design methodologies and design flows; and (4) physical design of industry leading system-on-chip (SoC).#0000

## Description

Work on the Physical Design aspects of the system-on-chip (SoC) delivery. Work with RTL/logic designers to drive architectural feasibility studies. Explore power performance-area tradeoffs for physical design closure at the block and Sub System level. Contribute to developing physical design methodologies & design flows. Drive physical design flow automation scripts using Tcl, Perl and/or Python. Carry the assigned block/partition physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off. Work closely with third party design and fabrication services to deliver quality first pass silicon that meets all performance, power and area goals. Create push button flows for RTL2GDS. Establish a regression flow that is triggered by new RTL check-in. Create automation for distributing various runs to LSF grid and for
viewing server CPU/Memory usage for Vendor license management and Usage. Define and develop signoff methodology and corresponding implementation solution for Static Timing Analysis (STA). Participate in full chip timing constraints development, full chip / Sub-System STA and Signoff for a complex, multi-clock, multi-voltage SoC. Streamline the timing signoff criterions, timing analysis methodologies and flows.


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