> Markdown version of [/jobs/ext/1952126-fpga-and-dsp-engineers](https://www.wearedevelopers.com/jobs/ext/1952126-fpga-and-dsp-engineers). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # FPGA and DSP Engineers - **Company:** Indotronix International Corporation - **Location:** Cedar Rapids, IA, United States - **Contract:** Permanent contract - **Skills:** Unix, C++ (Programming Language), Computer Engineering, Digital Architecture, Digital Technology, Perl (Programming Language), Field-Programmable Gate Array (FPGA), Signal Processing, Static Timing Analysis, SystemVerilog, Verilog, VHSIC Hardware Description Language (VHDL), Scripting, Application Specific Integrated Circuits, ModelSim, SC Clearance - **Published:** August 6, 2026 - **Apply:** https://www.clearancejobs.com/jobs/9078318/fpga-and-dsp-engineers ## About the Role Active Secret clearance at start - Bachelor's degree in Electrical Engineering, Computer Engineering, or related field - Expertise in FPGA design and/or verification - Strong VHDL experience - Proficiency with Intel/Altera FPGA tools (preferred), Modelsim, Synopsys, and/or FPGA vendor toolchains - Experience with high speed digital systems, interfaces, and signal processing - Strong hands on lab experience (non negotiable) Desired Skills - SystemVerilog + UVM verification - ASIC experience (nice-to-have) - Design-for-Test (DFT) and manufacturability knowledge - Unix/Linux, scripting, C/C++, or Perl experience ## Description 2-3 FPGA Design Engineers per 1 Verification Engineer - Approx. 8-10 engineers needed in El Segundo and Fullerton - 2 -3 may be placed in Cedar Rapid Design or verification backgrounds to contribute across requirements capture, digital architecture, RTL design, verification, and lab integration. Design & Architecture: - Requirements capture and development of FPGA/ASIC digital architectures - RTL design and implementation in VHDL or Verilog - Timing analysis and closure on high speed digital systems - Resource trade off analysis and design optimization Verification: - Testbench development using VHDL or SystemVerilog / UVM - Functional verification of RTL blocks and subsystems - Support constrained-random, functional coverage, and best practice verification methodologies ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [WeAreDevelopers LIVE - Node and Package Security](https://www.wearedevelopers.com/videos/2138-wearedevelopers-live-node-and-package-security) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [The Time Paradox: Building Timezone-Safe Python/Django Applications](https://www.wearedevelopers.com/videos/1915-the-time-paradox-building-timezone-safe-python-django-applications) - [Coffee with Developers - Robby Russell](https://www.wearedevelopers.com/videos/917-coffee-with-developers-robby-russell) - [How to Domain Model – An example from manufacturing](https://www.wearedevelopers.com/videos/742-how-to-domain-model-an-example-from-manufacturing) ## Related Articles - [Dev Digest 134 - Where pixels sing?](https://www.wearedevelopers.com/magazine/477-dev-digest-134-where-pixels-sing) - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Should senior developers refuse interview coding challenges?](https://www.wearedevelopers.com/magazine/29-should-senior-developers-refuse-interview-coding-challenges) - [Steps to Get a Software Engineer Internship](https://www.wearedevelopers.com/magazine/160-steps-to-get-a-software-engineer-internship) - [Dev Digest 171: AI in disguise, Doomed tech and system prompts](https://www.wearedevelopers.com/magazine/594-dev-digest-171-ai-in-disguise-doomed-tech-and-system-prompts)