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# Design Engineer III

- **Company:** Everforth Apex
- **Location:** Sunnyvale, CA, United States
- **Salary:** $145,600.0 - $166,400.0
- **Contract:** Permanent contract
- **Skills:** Data Analysis, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Perl (Programming Language), Formal Verification, Python (Programming Language), Machine Learning, SystemVerilog, Information Technology
- **Published:** August 6, 2026
- **Apply:** https://www.dice.com/job-detail/7be5353a-82af-4001-b75d-d0d5dc24565e

## About the Role

Education: A Bachelor of Science in Electrical/Computer Engineering or Computer Science is required., * Proven SystemVerilog and UVM verification experience, including testbench architecture, sequences, and drivers/monitors.

 * Experience with functional coverage, constrained-random, and assertion-based verification (SVA) and coverage closure.
 * Strong RTL debug skills with industry simulators (VCS, Xcelium, or Questa) and waveform tools like Verdi.
 * Working knowledge of RTL design principles and digital design fundamentals.
 * Proficiency in Python or Perl scripting for automation., * An MS in a relevant field is preferred.
 * Experience with power measurement tools such as PrimeTime PX (PTPX) or equivalent.
 * Experience with low-power or power-aware verification (UPF, power-aware simulation) in advanced nodes (7nm and below).
 * Formal verification or emulation (Palladium / Zebu) experience.
 * Familiarity with the RTL-to-GDSII flow.
 * Experience with data analysis or machine learning approaches for coverage or debug triage.

## Description

This position is for a Design Verification engineer focused on wearables silicon accelerator IPs. The role involves testbench development, coverage-driven verification, RTL debug, and power and performance measurement. The successful candidate will work with a small team to build and run testbenches, analyze coverage, debug failures, and measure power and performance., * Develop and execute verification plans for RTL blocks and IPs across the subsystem.

 * Build and maintain SystemVerilog/UVM testbenches, and write directed and constrained-random tests.
 * Drive functional coverage and assertion (SVA) closure, and run and triage regressions.
 * Perform power and performance measurement across design stages using specified tools and correlate results with post-silicon data.
 * Build a power and performance dashboard for tracking and publishing results.
 * Debug RTL failures using waveform tools and provide feedback to the design and verification teams.
 * Contribute to the automation of verification, regression, and power/performance measurement flows using Python.


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