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# DFT Engineer, Google Cloud

- **Company:** Google LLC
- **Location:** Sunnyvale, CA, United States
- **Experience:** Experienced
- **Salary:** $138,000.0 - $198,000.0
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Electronic Design Automation, Joint Test Action (IEEE Standards), Google Cloud, System-level Testing, Information Technology
- **Published:** August 6, 2026
- **Apply:** https://dejobs.org/x/x/B7518F408BA947C68BF5BB58DBD21339/job/

## About the Role

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area., * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

 * 3 years of experience in DFT architecture, implementation, Automatic Test Pattern Generation (ATPG), and verification for SoCs.
 * Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT)., * Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
 * Experience in DFT flow, including architecture, IP integration (Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.
 * Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, TestKompress).
 * Experience with silicon process and technology nodes for high speed and low power consumption.
 * Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.).

## Description

* Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality.
 * Insert DFT logic, including scan chains, MBIST, Test Access Port (TAP) controller, Clock Control block, and other DFT IP blocks.
 * Insert and hook up MBIST logic including test collar around memories, MBIST controllers, electronic fuse (eFuse) logic and connect to core and TAP interfaces.
 * Design Verification of DFT logic and test pattern generation.
 * Design and Implement System Level Test strategy.


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