> Markdown version of [/jobs/ext/1958725-sr-datacenter-gpu-lead-power-constrained-performance-architect](https://www.wearedevelopers.com/jobs/ext/1958725-sr-datacenter-gpu-lead-power-constrained-performance-architect). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

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# Sr Datacenter GPU Lead Power Constrained Performance Architect

- **Company:** Advanced Micro Devices, Inc.
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Salary:** $178,400.0
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, Artificial Intelligence, Boolean Algebra, Computer Engineering, Data Centers, Software Debugging, Rollup, Large Language Models, Information Technology, Power Analysis (Cryptography), Physical Design
- **Published:** August 6, 2026
- **Apply:** https://diversityjobs.com/main/sendform/8/8/28176/1/17829462?backUrl=%2Fcareer%2F17829462%2FSr-Datacenter-Gpu-Lead-Power-Constrained-Performance-Architect-Texas-Austin

## About the Role

* Background in Computer Architecture, Processor/Accelerator development
 * Experience in Power/Performance projections, modeling and optimization at SoC or System level
 * Familiarity with digital logic physical design and power management techniques (clock gating, power gating, V-F curves, p-states, on-die voltage regulation, clock integrity, etc..)
 * Familiarity with post-silicon power/performance debug, model correlation
 * Fluency in communicating with various engineering teams, business leads and executive management
 * Knowledge of DL/ML/LLM/MoE workloads will be a bonus
EDUCATION:

 * Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or related

## Description

* Own power-constrained performance modeling, projections, implementation target setting and attainment tracking from Concept-exit (pre-si) to Product launch (post-si) for AMD Instinct AI/ML/HPC accelerators
 * Work with business unit and product architecture to define product configurations, capabilities and P&P targets
 * Cross functionally lead P&P attainment by working with various engineering functions including SOC architecture, System Design, IP Design, Circuit Design, Foundry team, CAD, Physical Design, Software, Power Management, Post-si validation
 * Roll-up Power/Performance readouts, present in executive forums, motivate cross-functional teams on power efficiency improvements
 * Mentor junior engineers and develop skillsets and methodologies in the team for important PPA domains like Power Modeling at various stages of SoC development, Cdyn/Leakage/STA/Area trade-offs and attainment, Silicon Power/Performance debug, Post Si calibration of models, Work-load power analysis, AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.


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