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# Senior Design and Integration Engineer, Cloud TPU

- **Company:** Google LLC
- **Location:** Sunnyvale, TX, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Cloud Computing, Computer Networks, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Firmware, Information Technology, Hardware Acceleration, Physical Design, Hardware Debugging
- **Published:** August 7, 2026
- **Apply:** https://us.experteer.com/career/view-jobs/senior-design-and-integration-engineer-cloud-tpu-sunnyvale-tx-usa-58831477

## About the Role

complex and enhancement of internal design tools, flows, and methodologies * Own design deliverables, integration efforts, and methodological improvements Tasks * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience * 8 years of experience in RTL design * Experience with digital design and microarchitecture design * Experience in optimizing for performance, power, and area * Cross-functional experience with DV and PD teams Key requirements * bonus target * equity * benefits

## Description

Experteer Overview In this role you will shape the microarchitecture and RTL for Google's TPU digital designs. You will collaborate with Verification, Physical Design, Validation, and Firmware to meet timing, area, and power goals while supporting post-silicon debugging. You'll drive power optimization and automation across the on-chip network and subsystems and contribute to design tooling and engineering flows. This is a chance to work at scale on AI/ML hardware accelerators that power Google's AI stack. You will own key design deliverables and help integrate complex digital blocks into the TPU ecosystem. Compensation / Benefits * Define and document microarchitecture for TPU digital designs * Partner with Verification to develop test plans and debug RTL * Collaborate with Physical Design to achieve timing, area, and power targets * Drive critical power optimization and automation across on-chip-network components * Support post-silicon validation and hardware debugging * Lead development and enhancement of internal design tools, flows, and methodologies * Own design deliverables, integration efforts, and methodological improvements Tasks * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience * 8 years of experience in RTL design * Experience with digital design and microarchitecture design * Experience in optimizing for performance, power, and area * Cross-functional experience with DV and PD teams Key requirements * bonus target * equity * benefits


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