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# ASIC/SOC DFT Engineer (Silicon Engineering)

- **Company:** Space Exploration Technologies Corp.
- **Location:** Palo Alto, CA, United States
- **Contract:** Permanent contract
- **Skills:** Bash Shell, Computer Engineering, Software Debugging, Perl (Programming Language), Formal Verification, Python (Programming Language), SystemVerilog, Verilog, Scripting, Application Specific Integrated Circuits, Information Technology, Physical Design
- **Published:** August 7, 2026
- **Apply:** https://us.experteer.com/career/view-jobs/asic-soc-dft-engineer-silicon-engineering-palo-alto-ca-usa-58832808

## About the Role

integrate with circuit physical design, ATPG, and manufacturing teams to ensure high-quality silicon Tasks * Bachelor's degree in electrical engineering, computer engineering or computer science * 1+ years of professional ASIC experience * Experience in scan insertion or DFT setup * Desirable: understanding of ASIC design flow, physical design, and verification * Scripting skills (csh/bash, Perl, Python) * Verilog/SystemVerilog knowledge * UPF, formal verification, DRC exposure Key requirements * Comprehensive medical, vision, dental

## Description

Experteer Overview In this role you will help design and verify cutting-edge ASICs for SpaceX's Starlink platforms, spanning space and ground infrastructure. You'll work with cross-disciplinary teams to integrate DFT fabrics and ensure robust testability of silicon devices. The position challenges you to optimize scan insertion, ATPG, and test flows to enable reliable, high-performance connectivity. This opportunity lets you impact global satellite internet scale and future space missions. Compensation / Benefits * Evaluate design readiness for scan insertion through RTL and physical design * Integrate and verify Design for Test (DFT) fabrics and IP within subsystems * Run and optimize scan insertion through synthesis tools for maximum coverage * Execute ATPG analysis to ensure quality scan chain construction and coverage goals * Run non-timing and SDF-annotated gate-level simulations and debug * Create ATPG content for post-silicon testing and validate via gate-level simulation * Collaborate with circuit physical design, ATPG, and manufacturing teams to ensure high-quality silicon Tasks * Bachelor's degree in electrical engineering, computer engineering or computer science * 1+ years of professional ASIC experience * Experience in scan insertion or DFT setup * Desirable: understanding of ASIC design flow, physical design, and verification * Scripting skills (csh/bash, Perl, Python) * Verilog/SystemVerilog knowledge * UPF, formal verification, DRC exposure Key requirements * Comprehensive medical, vision, dental


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