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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # ASIC Engineer - Remote - **Company:** Purple Hires - **Location:** Plano, TX, United States (Remote available) - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Code Coverage, Software Debugging, Electronic Design Automation, Perl (Programming Language), Joint Test Action (IEEE Standards), Python (Programming Language), Static Timing Analysis, Tcl (Programming Language), Application Specific Integrated Circuits, Physical Design - **Published:** August 7, 2026 - **Apply:** https://www.careerjet.com/jobad/us9ff1ed515bad0f9d5074a25a54387bb3 ## About the Role please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield., Strong hands-on experience in ASIC DFT with end-to-end ownership. Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts. Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug. Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools. Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis. Experience with MBIST implementation and verification; SMS experience preferred. Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred. Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation. Proven post-silicon debug and silicon bring-up experience. Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges. Strong communication skills and the ability to work independently with minimal ramp-up. Preferred Experience MBIST post-silicon validation. ATPG simulations and fault coverage debug. DFT RTL, DFD, DFT verification, and IP-level DFT integration. DFT SDC creation and DFT timing closure support. Boundary scan, iJTAG, SSN, and design-for-debug methodologies. TCL/PERL scripting for DFT automation, reporting, and debug. Experience working across multiple ASIC technology nodes and complex product development cycles. Familiarity with yield learning, diagnosis, and manufacturing test optimization. ## Description Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs. Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability. Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases. Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues. Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis. Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues. Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality. Act as a technical escalation point for advanced DFT and post-silicon debug issues. Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation. Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity. ## Related Videos - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Mutation Testing and Fuzzing in C#](https://www.wearedevelopers.com/videos/703-mutation-testing-and-fuzzing-in-c) - [Building a fully automated escape room](https://www.wearedevelopers.com/videos/735-building-a-fully-automated-escape-room) - [Using AI Without Losing Your Skills](https://www.wearedevelopers.com/videos/2045-using-ai-without-losing-your-skills) - [Breaking the Bug Cycle: TDD for the Win](https://www.wearedevelopers.com/videos/1037-breaking-the-bug-cycle-tdd-for-the-win) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) ## Related Articles - [Fully Remote Software Engineer Jobs](https://www.wearedevelopers.com/magazine/447-fully-remote-software-engineer-jobs) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Should senior developers refuse interview coding challenges?](https://www.wearedevelopers.com/magazine/29-should-senior-developers-refuse-interview-coding-challenges) - [Where To Find Software Engineering Jobs](https://www.wearedevelopers.com/magazine/396-where-to-find-software-engineering-jobs) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline)