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# MTS, AI Optimized Memory Digital Design Engineer

- **Company:** Micron Technology, Inc.
- **Location:** Folsom, CA, United States
- **Experience:** Expert
- **Salary:** $175,000.0 - $309,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, C++ (Programming Language), Computer Engineering, Logic Synthesis of Circuits, Python (Programming Language), SystemVerilog, Information Technology, Virtual Agents, Programming Languages
- **Published:** August 7, 2026
- **Apply:** https://www.techcareers.com/job.asp?id=3343324760&tx=CT2927TTZ&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field
 * Strong experience in digital design and microarchitecture development with ownership of hardware blocks from specification through implementation
 * Solid understanding of computer architecture and memory systems, including SoC-level behaviors and tradeoffs
 * Experience with synthesis flows and early PPA estimation and optimization
 * Proficiency in SystemVerilog and at least one programming language such as C, C++, or Python, * Master's or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience
 * 5+ years of industry experience delivering silicon-proven memory systems or SoC hardware designs on modern process nodes
 * Familiarity with memory interfaces, reliability features, and media management concepts
 * Experience influencing architecture features with a strong understanding of RTL implementation cost and feasibility
 * Experience working with Agentic AI tools to assist with design and verification

## Description

* Translate architecture requirements into scalable microarchitectures and drive implementation from concept through silicon
 * Design, implement, and review SystemVerilog RTL for advanced memory system architectures
 * Perform synthesis and early PPA analysis to optimize area, power, and timing
 * Develop and maintain microarchitecture documentation that aligns design intent across teams
 * Evaluate architectural and implementation tradeoffs to support technical decision-making


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