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# Principal Firmware/Middleware Engineer

- **Company:** Renesas Electronics America, Inc.
- **Location:** San Jose, CA, United States
- **Contract:** Permanent contract
- **Skills:** Application Programming Interfaces (APIs), Artificial Intelligence, Computer Engineering, Software Debugging, Middleware, Embedded Software, Firmware, FreeRTOS, Joint Test Action (IEEE Standards), Python (Programming Language), Routing, PCI Express, Real-Time Operating Systems, Dynamic Routing, Application Specific Integrated Circuits, State Machines, Information Technology, Low Latency, Bare Metal, Trace32
- **Published:** August 7, 2026
- **Apply:** https://us.experteer.com/career/view-jobs/principal-firmware-middleware-engineer-san-jose-ca-usa-58826217

## About the Role

* Design deterministic link-training state machines for ultra-high-speed connections * Develop runtime topology discovery, dynamic routing, and credit management * Lead platform orchestration with SDKs/APIs for OpenBMC/Redfish-based management * Tune bare-metal paths to ensure deterministic low latency for collective ops * Design robust RAS architectures with telemetry and fault isolation * Implement secure boot, cryptographic authentication, and runtime attestation to ensure fabric integrity * Develop security measures around Root of Trust and attestation Tasks * Degree: Bachelor's, Master's, or PhD in Computer Engineering, Electrical Engineering, or Computer Science * 15+ years of hands-on embedded systems or low-level firmware experience * Expert in C for bare-metal/RTOS environments (ThreadX, FreeRTOS, Zephyr) * Proficient in Python for hardware automation/modeling * Deep understanding of high-speed interconnect protocols (UALink, NVLink, CXL, PCIe Gen5/Gen6) * Solid knowledge of a
attestation flow control, routing, PHY equalization, and SerDes management * Experience with hardware debuggers (JTAG, Lauterbach TRACE32) and lab tools (Oscilloscopes, PCIe/Protocol Analyzers) * Strong collaboration and communication with cross-functional teams Key requirements * bonus opportunities * competitive benefits package * salary range $230,000-$270,000 * opportunity to work on world-leading technology * equal opportunity employer

## Description

Experteer Overview As Principal Firmware Architect, you will define and drive the end-to-end firmware and embedded software architecture for next-generation AI cluster switch fabric. You will bridge silicon and software, shaping how firmware manages high-speed interconnects, latency-critical primitives, and robust fabric reliability across thousands of accelerators. You'll collaborate with ASIC, RTL, and verification teams to deliver deterministic, scalable firmware and SDKs/APIs for BMC-driven orchestration. This role offers impact in a high-performance, security-conscious environment with opportunities to mold the fabric that powers AI clusters. Compensation / Benefits * Architect fabric firmware and low-level firmware running on UALink ASIC microcontrollers * Define hardware-software interfaces, registers, scratchpads, and memory maps in collaboration with ASIC/RTL/verification teams * Specify firmware stack for physical, link, and transport layers including flow control and routing * Design deterministic link-training state machines for ultra-high-speed connections * Develop runtime topology discovery, dynamic routing, and credit management * Lead platform orchestration with SDKs/APIs for OpenBMC/Redfish-based management * Tune bare-metal paths to ensure deterministic low latency for collective ops * Design robust RAS architectures with telemetry and fault isolation * Implement secure boot, cryptographic authentication, and runtime attestation to ensure fabric integrity * Develop security measures around Root of Trust and attestation Tasks * Degree: Bachelor's, Master's, or PhD in Computer Engineering, Electrical Engineering, or Computer Science * 15+ years of hands-on embedded systems or low-level firmware experience * Expert in C for bare-metal/RTOS environments (ThreadX, FreeRTOS, Zephyr) * Proficient in Python for hardware automation/modeling * Deep understanding of high-speed interconnect protocols (UALink, NVLink, CXL, PCIe Gen5/Gen6) * Solid knowledge of credit-based flow control, routing, PHY equalization, and SerDes management * Experience with hardware debuggers (JTAG, Lauterbach TRACE32) and lab tools (Oscilloscopes, PCIe/Protocol Analyzers) * Strong collaboration and communication with cross-functional teams Key requirements * bonus opportunities * competitive benefits package * salary range $230,000-$270,000 * opportunity to work on world-leading technology * equal opportunity employer


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