> Markdown version of [/jobs/ext/1982016-senior-digital-ip-design-engineer](https://www.wearedevelopers.com/jobs/ext/1982016-senior-digital-ip-design-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior Digital IP Design Engineer - **Company:** NXP Semiconductors - **Location:** München, Germany - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Adobe Flash, Adobe InDesign, Artificial Intelligence, Systems Engineering, Bash Shell, C++ (Programming Language), Software Debugging, Logic Synthesis of Circuits, Microprocessors, Perl (Programming Language), Python (Programming Language), CPU Design, Reduced Instruction Set Computing, Static Timing Analysis, SystemVerilog, Systems Integration, Tcl (Programming Language), Verilog, Scripting, Information Technology - **Published:** August 8, 2026 - **Apply:** https://eu.experteer.com/career/view-jobs/senior-digital-ip-design-engineer-f-m-d-muenchen-bayern-deutschland-58835527 ## About the Role and with standard tools * Lead IP-level verification activities including basic testbench development and simulations * Conduct IP synthesis and basic timing analysis to meet targets * Ensure design for testability (DFT) compliance * Generate design documentation and participate in design reviews * Troubleshoot design issues throughout the lifecycle * Stay updated with industry trends and tools in digital design Tasks * Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field * Minimum 5 years of IP or subsystem design experience * Solid understanding of microprocessor architecture, interconnects, and cache coherency * Hands-on CPU design experience (proprietary cores, RISC-V, or AI/ML accelerators) * Experience with AI-based tools to enhance development * Experience with AMBA protocols (AHB, AXI, ACE, CHI) and memory systems (ROM, RAM, Flash, DDR/LPDDR) * Advanced knowledge of Verilog, SystemVerilog, and C/C++ * Proficiency in scripting (Python, aaa in TCL, Shell) * Experience debugging in pre-silicon and post-silicon environments * Strong analytical and problem-solving skills * Excellent English communication; basic German a plus * Security-related task potential and certifications awareness Key requirements * ## Description Experteer Overview In this role, you will design and implement digital IP and RTL for complex mixed-signal SoCs, focusing on performance, area, and power targets. You will collaborate with hardware, software, and architecture teams to define features and interfaces and ensure system-level integration. You'll perform RTL design, linting, basic verification, synthesis, and timing analysis, while aligning with design-for-testability and documentation practices. You will contribute to security-related tasks when required, staying current with industry trends. This is a hands-on, cross-functional role in a leading Munich chip team that shapes next-gen AI/ML and RISCV IPs. Pay / Benefits * Develop and implement digital IP and RTL for complex mixed-signal SoCs * Collaborate with hardware, software, architecture, and system engineering teams to define features and interfaces * Create area-efficient, low-power RTL designs using Verilog/SystemVerilog * Perform design quality checks (Lint, CDC/RDC) with standard tools * Lead IP-level verification activities including basic testbench development and simulations * Conduct IP synthesis and basic timing analysis to meet targets * Ensure design for testability (DFT) compliance * Generate design documentation and participate in design reviews * Troubleshoot design issues throughout the lifecycle * Stay updated with industry trends and tools in digital design Tasks * Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field * Minimum 5 years of IP or subsystem design experience * Solid understanding of microprocessor architecture, interconnects, and cache coherency * Hands-on CPU design experience (proprietary cores, RISC-V, or AI/ML accelerators) * Experience with AI-based tools to enhance development * Experience with AMBA protocols (AHB, AXI, ACE, CHI) and memory systems (ROM, RAM, Flash, DDR/LPDDR) * Advanced knowledge of Verilog, SystemVerilog, and C/C++ * Proficiency in scripting (Python, Perl, TCL, Shell) * Experience debugging in pre-silicon and post-silicon environments * Strong analytical and problem-solving skills * Excellent English communication; basic German a plus * Security-related task potential and certifications awareness Key requirements * ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Old tools, new tricks](https://www.wearedevelopers.com/videos/1916-old-tools-new-tricks) - [JavaScript? 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