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# DMTS NOC Cache Coherency Architect

- **Company:** GF U.S. Inc.
- **Location:** Richardson, TX, United States
- **Experience:** Expert
- **Salary:** $166,500.0 - $290,000.0
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Computer Engineering, Perl (Programming Language), Field-Programmable Gate Array (FPGA), Python (Programming Language), Multiprocessing, Reduced Instruction Set Computing, SystemVerilog, Tcl (Programming Language), Verilog, Network Switches, Scripting
- **Published:** August 8, 2026
- **Apply:** https://globalfoundries.wd1.myworkdayjobs.com/External/job/Richardson/Lead-NOC-Cache-Coherency-Architect_JR-2600347

## About the Role

MIPS - A GlobalFoundries company is seeking a highly experienced NOC and Cache Coherency Architect with over 15 years of industry experience to lead design efforts focused specifically on NOC, Coherency Manager and Cache Controller components.

The successful candidate will have extensive hands-on experience utilizing advanced design methodologies. This senior role involves close collaboration with CPU core architects, designers, and cross-functional global teams to ensure high-quality, high-performance processor designs., * Master's degree or higher in Electronics/Electrical/Computer Engineering.

 * 15+ years of relevant verification experience, specifically in CPU or complex SoC verification.
 * Proven expertise in Multicore and Multicluster Coherency, Cache Controllers, or similar blocks.
 * Proficiency in SystemVerilog, Verilog, C/C++, and Assembly.
 * Solid understanding of interconnect and coherency protocols such as AXI, ACE, OCP, CHI.
 * Strong scripting skills in Python, Perl, TCL, or Shell.
 * Experience with CPU architectures, particularly RISC-V, ARM, or MIPS., * Experience with RISC-V architecture.
 * Familiarity with functional safety standards (e.g., ISO 26262).
 * Prior exposure to FPGA prototyping and emulation platforms.

## Description

* Lead and drive architectural specification and design activities for Coherency Manager and Cache Controller IP to closure.
 * Collaborate closely with design teams and architects to thoroughly understand and interpret microarchitectural and functional specifications.
 * Automate and optimize verification flows and regression environments using scripting languages like Python, Perl, TCL, or Shell.
 * Mentor design engineers, providing technical guidance and leadership within the verification team.

Other Responsibilities:

· Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.


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