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# R&D Digital Design Engineer

- **Company:** Broadcom
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $121,900.0 - $195,000.0
- **Contract:** Permanent contract
- **Skills:** Cloud Computing, Computer Engineering, Microarchitecture, Data Centers, Software Debugging, Logic Synthesis of Circuits, Ethernet, High-Level Architecture, Multi-protocol Systems, Python (Programming Language), Network Protocols, Parsing, Program Design Languages, TCP/IP, Network Switches, Scripting, Application Specific Integrated Circuits, Information Technology
- **Published:** August 8, 2026
- **Apply:** https://www.sanjosejobsite.com/job.asp?id=3347470800&tx=YT707CTZ&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

The ideal candidate should exhibit the following behavioral traits

 * Thoughtful and perceptive analytical ability.
 * A genuine curiosity for understanding the complete system.
 * Dedicated to creative problem solving.
 * ability to work independently and at various levels of abstraction.
 * Committed to getting things done and executing to plan, * B.S. in electrical engineering, computer engineering, computer science, or equivalent.
 * B.S. with 8 years of experience, or M.S with 5 years of experience in digital design on multiple networking ASICs.
 * 5+ years of experience in verilog based rtl design or verification, in deep submicron technologies.
 * Familiarity with Ethernet and other networking protocols., * Extensive experience with Ethernet, TCP/IP, MPLS, tunneling, and other networking protocols.
 * Extensive experience with packet processing architectures (packet parsing, acls, metering, policing, etc.)
 * Experience achieving timing closure on high performance ASICs in deep submicron technologies.
 * Experience with low power design techniques, power estimation methods, clock domain crossing techniques.
 * Experience with scripting languages, such as python or perl.

## Description

The core switch group (csg) at broadcom focused on developing high-performance ethernet switch silicon and software, primarily targeting hyperscale data centers, cloud providers, and enterprise networks. our group is recognized as an

industry leader in merchant silicon, enabling massive network bandwidth for ai infrastructure and cloud applications.

Our organization works on all levels of ASIC development, spanning high-level architecture to RTL design and verification and volume manufacturing. We are looking for a motivated and astute individual to join our team as a logic design engineer.as a logic design engineer you will use your knowledge of specifications, mathematics, and computation to write efficient and elegant rtl for implementing components of complex networking asics.

This role requires participation through the full program design lifecycle: developing micro-architecture specifications, RTL implementation, Unit verification, Timing convergence, ECO implementation, debug analysis and reviews.


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