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# Software Engineer - Vendor Integrations

- **Company:** Axelera AI
- **Location:** UK (Remote available)
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Bash Shell, Software Debugging, Electronic Design Automation, Formal Verification, Python (Programming Language), Static Timing Analysis, Tcl (Programming Language), Scripting, AI Platforms, Physical Verification, Physical Design, Cts+
- **Published:** August 9, 2026
- **Apply:** https://www.workingnomads.com/job/go/1780807/

## About the Role

* 10+ years of experience in Physical Design (RTL to GDS).
 * Strong communication and teamwork skills.
 * Expertise in all aspects of physical design.
 * Hands-on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre).
 * Proficiency in clocking techniques and CTS.
 * Experience in IP integration across various domains.
 * Strong scripting skills (Python and Tcl).
 * Proven problem-solving and debugging capabilities.
 * Fluent in English (spoken and written).

Highly preferred:

 * Experience in floorplanning and top level integration.
 * Knowledge of chip-package-board co-simulation and packaging.
 * Experience working with EDA vendors to resolve tool issues.
 * Understanding of semiconductor device physics and multi-domain design.

## Description

As a Senior/Staff Silicon Physical Design Engineer at Axelera AI, you will play a crucial role in developing cutting-edge multi-core in-memory compute SoCs. Leveraging your expertise in ASIC Physical Design from RTL to GDS, you will be responsible for all aspects, including synthesis, floorplanning, place and route, extraction, timing analysis, physical verification, EMIR signoff, and formal verification. You will collaborate closely with architecture and RTL teams to ensure successful project execution., * Perform synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification.

 * Constraint generation, timing analysis and optimization.
 * Execute clock tree synthesis (CTS) and custom clock-building techniques.
 * Integrate IPs including memories, I/Os, embedded processors, DDR, networking fabrics, and analog IPs.
 * Utilize EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre.
 * Develop automation scripts in Python, Tcl, Bash and contribute to flow development.
 * Debug and solve technical challenges related to physical design.
 * Collaborate with architecture, RTL, and verification teams.


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