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# Senior ASIC DV Engineer

- **Company:** Broadcom
- **Location:** Irvine, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Software Debugging, Microprocessors, Field-Programmable Gate Array (FPGA), Mobile Application Software, Broadcom, Scripting, Application Specific Integrated Circuits
- **Published:** August 9, 2026
- **Apply:** https://us.experteer.com/career/view-jobs/senior-asic-dv-engineer-irvine-ca-usa-58868286

## About the Role

to ASIC validation * Replicate silicon bugs in simulation and validate fixes or SW workarounds * Convert verification tests to test patterns and assist Test Engineers on ATE vector bring-up * Automate verification flows by evaluating and developing scripts and methodologies * Apply knowledge of low power silicon for mobile applications and UPF low power verification flow * Take customer requirements to verify full chip design and architecture Tasks * Bachelor's in Engineering with 12+ years of related experience; or Master's in Engineering with 10+ years; or PhD in Engineering with 7+ years * MS or PhD preferred Key requirements * Medical, dental and vision plans * 401(K) with company matching * Employee Stock Purchase Program (ESPP) * Employee Assistance Program (EAP) * company paid holidays * paid sick leave and vacation

## Description

Experteer Overview As a Verification Engineer at Broadcom, you will help develop complex SOC verification environments for touch controllers and wireless charging chips. You will work with cross-functional teams to ensure robust block and full-chip validation, including low-power considerations. You will translate specifications into test plans, debug RTL/gate simulations, and validate fixes on silicon-like environments. This role offers hands-on impact from pre-tapeout prototypes to post-silicon readiness, with opportunities to advance verification methodologies. Compensation / Benefits * Architect block- and full-chip verification environments using HVLs/UVM and constrained random techniques for SOCs with embedded CPUs and mixed-signal interfaces * Develop test plans and coverage metrics from specifications and write block- and chip-level tests * Debug RTL and gate simulations and collaborate with design engineers to verify fixes * Write diagnostics for FPGA prototype (pre-tapeout) and ASIC validation * Replicate silicon bugs in simulation and validate fixes or SW workarounds * Convert verification tests to test patterns and assist Test Engineers on ATE vector bring-up * Automate verification flows by evaluating and developing scripts and methodologies * Apply knowledge of low power silicon for mobile applications and UPF low power verification flow * Take customer requirements to verify full chip design and architecture Tasks * Bachelor's in Engineering with 12+ years of related experience; or Master's in Engineering with 10+ years; or PhD in Engineering with 7+ years * MS or PhD preferred Key requirements * Medical, dental and vision plans * 401(K) with company matching * Employee Stock Purchase Program (ESPP) * Employee Assistance Program (EAP) * company paid holidays * paid sick leave and vacation


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