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# Principal ASIC Lead

- **Company:** Space Exploration Technologies Corp.
- **Location:** Irvine, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Microarchitecture, Perl (Programming Language), Formal Verification, Integrated Development Environments, Python (Programming Language), Shell Script, Static Timing Analysis, SystemVerilog, VHSIC Hardware Description Language (VHDL), Application Specific Integrated Circuits, Backend, Power Analysis (Cryptography), Physical Design
- **Published:** August 9, 2026
- **Apply:** https://www.wayup.com/i-j-spacex-289224995928440/

## About the Role

+ BS in Electrical Engineering
 + 10+ years of front-end ASIC experience
 + Must have put a minimum of 3 ASICs into high volume production
 + 4+ years experience managing and leading small teams
 + Previous experience with System Verilog & VHDL coding, Synthesis, Formal Verification, Static Timing Analysis
 + Previous experience with Python, Perl, Shell scripting experience
PREFERRED SKILLS AND EXPERIENCE:

 + Masters of Science in Electrical Engineering
 + Low power design experience or concepts including power estimation, tradeoffs between varied options, etc.
ADDITIONAL REQUIREMENTS:

 + Must be available to work extended hours and weekends as needed
ITAR REQUIREMENTS:

 + To conform to U.S. Government space technology export regulations, applicant must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about ITAR here.

## Description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
PRINCIPAL ASIC LEAD
RESPONSIBILITIES:
Responsible for leading a ASIC program and team of ASIC design and verification engineers. Major responsibilities include providing technical leadership, project schedules and tracking, and managing external vendor relationships. Responsibilities include:

 + Participate in the design process starting with high-level conceptual and architectural discussions and ending with micro architecture and design partition within the ASIC.
 + Implement blocks using System Verilog and work with Verification Engineers to design the verification environment.
 + Oversee all aspects of development of the subsystem. For each functional area, collaborate with the local technical lead to assign tasks, monitor progress and track deliverables.
 + Synthesize designs and make sure there are no design rules violations using available lint tools.
 + Clear planning of project stages and identify critical milestones.
 + Work with backend teams to address layout and timing issues and to optimize the area of the circuit.
 + Assist with recruiting, coaching, and/or developing organizational talent.
 + Assist with interfacing with external ASIC vendors and overseeing all associated aspects of backend development including, but not limited to:
o Floor planning
o Physical Design
o DFT
o STA
o Power analysis
o Packaging

 + Promote a culture of innovation, collaboration, high-quality execution in a fast paced development environment


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