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# Product Performance Engineer

- **Company:** Hark's Co.
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $120,000.0 - $300,000.0
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Profiling, Computer Programming, Data Centers, Python (Programming Language), Model Validation, Information Technology
- **Published:** August 9, 2026
- **Apply:** https://www.adzuna.com/details/5833073687

## About the Role

* 5+ years analyzing workload behavior and modeling system performance for consumer or data center products
 * BS in Computer Science, Electrical Engineering, or related technical discipline
 * Hands-on experience with profiling, benchmarking, and tracing tools across the stack
 * Strong programming skills in Python and at least one systems language (C/C++/Rust)
 * Demonstrated ability to translate quantitative analysis into architectural recommendations

Bonus Qualifications

 * MS or PhD in a relevant technical discipline
 * Experience with hardware/software co-design and architectural exploration tooling
 * Familiarity with accelerator, SoC, or memory subsystem architecture
 * Comfort moving fluidly between rigorous quantitative work and cross-functional influence
 * Curiosity, technical depth, and a bias toward learning new system domains quickly

## Description

* Build deep understanding of target workloads and characterize their compute, memory, bandwidth, and latency demands on a variety of target hardware platforms
 * Model performance at every level - silicon, system, service, and end-to-end user experience - and connect insights across layers
 * Develop and maintain analytical and simulation-based models that project system performance across design and assumption variants
 * Collaborate with silicon, software, hardware, model, and service teams to align assumptions and deliver insights
 * Validate models against measured workload behavior and continuously improve fidelity
 * Translate findings into clear, actionable recommendations for architects, engineers, and leadership
 * Proactively identify performance risks and design opportunities ahead of architectural commit points


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