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# Lead Application Engineer

- **Company:** Cadence Design Systems, Inc.
- **Location:** Sacramento, CA, United States (Remote available)
- **Experience:** Expert
- **Salary:** $92,400.0 - $171,600.0
- **Contract:** Permanent contract
- **Skills:** Signal Integrity, Physical Design
- **Published:** August 10, 2026
- **Apply:** https://www.techcareers.com/job.asp?id=3348881725&tx=KJ3939FFF&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

The candidate will have expert knowledge of the Cadence toolset and/or equivalent competitor toolsets in the context of multiple flows including high-speed signal design, power design, signal integrity, power integrity and definition of electrical constraints. Design experience and industry knowledge of one of Signal, Power, and Thermal analysis associated with IC, package, or PCB design is required .

The candidate needs to have the ability to analyze the customer's environment and evaluate appropriate solutions. Be knowledgeable and aware of competitive technologies. Anticipates technical issues and develops creative solutions before they become a problem. Takes technical lead on a wide range of projects. Ability to understand high-speed, high-performance signal and power integrity-related issues, and work with peers and other business groups. Able to communicate effectively with Cadence R&D, Product Engineering, Marketing and with customers. Understands customer success criteria and is committed to ensuring customer success., Position requires:- Bachelor's degree (Masters preferred) in Electrical or Electronics Engineering with - Minimum 15 years experience with Signal Integrity, Power Integrity, Electromagnetics, Thermal, and RF related to Package and PCB Design is required- 5+ years experience with Cadence SI/PI tools Allegro platform tools including: Sigrity, Clarity, PCB Editor, ICP preferred- Strong knowledge of advanced packaging concepts- Strong knowledge of 2.5D, 3DIC and stacked die technologies- Understanding of chip level CMOS design concepts desired- Strong customer-facing communication and problem-solving skills- Strong personal drive for continuous learning and expanding professional skill sets- Excellent verbal and written communication skills



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