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# Principal Engineer DSP PHY Digital Design

- **Company:** Infineon Technologies AG
- **Location:** Dallas, TX, United States
- **Contract:** Permanent contract
- **Skills:** Algorithm Design, C++ (Programming Language), Computer Engineering, Data Transmissions, Software Debugging, Logic Synthesis of Circuits, Interoperability, Python (Programming Language), MATLAB, System Testing, IEEE 802.3, Low Latency
- **Published:** May 16, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=7b9bd07d7c5f45b7

## About the Role

Do you have experience in Statistics?, * B.S. + 10 years (or M.S. + 7 years) in Electrical Engineering, Computer Engineering, or related field

 * Strong fundamentals in digital communications and DSP, including probability/statistics
 * Practical experience in high-speed wireline DSP, including some mix of: FFE/DFE, adaptation, CDR, MLSD/Viterbi concepts, FEC integration, fixed-point modeling
 * Strong C++ and MATLAB skills for algorithm development, modeling, and analysis

Preferred qualifications

 * Experience with automotive Ethernet PHY/SerDes constraints(robustness, low latency, interoperability, EMI resilience)
 * Familiarity with ADC-based receiver architectures and calibration concepts
 * Experience translating algorithms into RTL-friendly specs(throughput/latency budgeting, memory/compute sizing, state-machine behavior)
 * Knowledge of link startup/training / autoneg concepts and system validation
 * Exposure to standards work (e.g., IEEE 802.3) or cross-company technical leadership

## Description

#WeAreIn for jobs that impact everyone's life. Build the future nobody's dreamed of yet... are you ready to rethink the impossible? As a Principal Engineer DSP PHY Digital Design in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. Are you in?, * Architect and simulate DSP signal chains for automotive Ethernet PHYs: define features, performance targets, and algorithm specs for mixed-signal and digital teams

 * RTL Design and Verification
 * Develop equalization and adaptation algorithms for wireline channels(e.g., FFE/DFE, adaptive filtering), including fixed-point considerations
 * Design and implement timing recovery/synchronization blocks (CDR, tracking loops), including jitter tolerance and stability/latency tradeoffs
 * Contribute to detection and coding / FEC integration: soft-information interfaces, performance/complexity tradeoffs, and linkKPIs
 * Build bit-true / fixed-point models and reference implementations primarily in C++ and MATLAB (Python optional, not core
 * Define verification metrics and stress tests (BER/FER, convergence time, corner cases) and partner with DV to ensure coverage Support silicon bring-up and lab debug: correlate model
 * silicon, root-cause issues, and iterate on algorithms/specs
 * Collaborate across architecture, design, verification, and applications to deliver implementable and testable solutions


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