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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # BIOS Engineer - **Company:** Monolithic Power Systems - **Location:** San Jose, CA, United States - **Experience:** Expert - **Salary:** $140,000.0 - $220,000.0 - **Contract:** Permanent contract - **Skills:** Board Bringup, C (Programming Language), Microsoft Windows, Advanced Configuration and Power Interface (ACPI), Adobe InDesign, Systems Engineering, Intelligent Platform Management Interface, Bash Shell, BIOS, C++ (Programming Language), Configuration Management, Computer Engineering, Continuous Delivery, Continuous Integration, Datasheets, Software Debugging, Device Drivers, Microprocessors, Dynamic Random-Access Memory, Firmware, Hardware Design, Interoperability, Joint Test Action (IEEE Standards), Python (Programming Language), PCI Express, Reduced Instruction Set Computing, Serial Communications, Subsystems, Systems Architecture, System Programming, System Testing, Universal Asynchronous Receiver/Transmitter, USB, Scripting, Extensible Firmware Interface, Git, Information Technology, U-Boot, Multiplatform, Software Version Control, Hardware Debugging - **Published:** August 10, 2026 - **Apply:** https://www.careerbuilder.com/job-details/staff-bios-platform-system-engineer-san-jose-ca--82bcf545-424a-43b2-9c91-3cd8d259ed25 ## About the Role * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field. * 3+ years of hands-on experience in BIOS/UEFI firmware development or validation. * Strong understanding of DDR5 memory architecture, training algorithms, SPD/MR registers, and RAS features is highly desired. * Demonstrated experience with at least two of the following CPU architectures: AMD (AGESA, EPYC/Ryzen), Intel (FSP, Core/Xeon), or ARM (TF-A, EDK2). * Proficiency in C/C++ and scripting languages (Python, Bash) for firmware development and automation. * Experience with UEFI/EDK2 framework, SMM, DXE, PEI driver development, and ACPI/ASL. * Familiarity with hardware debug tools: JTAG debuggers (Intel ITP, Lauterbach), protocol analyzers, oscilloscopes, and serial console interfaces. * Solid understanding of platform busses and interfaces: PCIe, USB, I2C/SMBus, SPI, LPC, UART, and GPIO. * Experience reading and interpreting hardware schematics, datasheets, and silicon vendor documentation. * Excellent analytical and problem-solving skills with the ability to work across hardware and software boundaries. * Strong written and verbal communication skills; experience authoring technical documentation., * Experience with AMD PSP, Intel ME/CSME, or ARM TrustZone security subsystems. * Familiarity with BMC firmware (OpenBMC) and IPMI/Redfish management interfaces. * Knowledge of server platform RAS features: DRAM ECC, memory mirroring, patrol scrub, and machine check architecture (MCA). * Exposure to PCIe Gen 5 or CXL 2.0/3.0 interconnect validation. * Hands-on experience with JEDEC DDR5 compliance testing and memory timing optimization. * Understanding of power management frameworks: ACPI, AMD STAPM, Intel DPTF, and platform telemetry. * Prior collaboration with silicon vendors (AMD, Intel, Arm Ltd.) on pre-silicon or early-silicon bring-up. * Experience with version control systems (Git), CI/CD pipelines, and agile engineering workflows. * Proficiency with Windows debugging environments for BIOS/firmware development., ARM (Advanced RISC Machine), Algorithms, Analysis Skills, Automation, Bash Scripting, Boundary Scan, C Programming Language, C++ Programming Language, CPU (Central Processing Unit), Chipset, Communication Skills, Computer Engineering, Computer Firmware, Computer Science, Continuous Deployment/Delivery, Continuous Integration, Cross-Functional, DRAM, Datasheets, Debugging Skills, Debugging Tools, Device Drivers, Diversity, Documentation, Electrical Engineering, Genetics, Git, Hardware Administration, Hardware Debugging, Hardware Design, I2C, IPMI (Intelligent Platform Management Interface), Identify Issues, Industry Standards, Instrumentation, Intel Product Family, Interoperability, Joint Electron Device Engineering Council (JEDEC), Logic Analyzer, Manufacturing, Memory Hardware, Memory Subsystem, Memory Testing, Microsoft Windows Operating System, Multiplatform/Cross-Platform, Oscilloscope, PCI Express (PCI-E), Power Management, Presentation/Verbal Skills, Problem Solving Skills, Protocol Analysis, Python Programming/Scripting Language, Schematics, Scripting (Scripting Languages), Semiconductors, Serial Link Design, Silicon Bringup, Source Code/Configuration Management (SCM), Sustainability, System Architecture, System Validation, Systems Engineering, Team Player, Technical Writing, Telemetry, Testing, USB, Universal Asynchronous Receiver-Transmitter (UART), Validation Plan, Validation Testing, Willing to Travel, Writing Skills ## Description We are seeking a skilled and motivated Senior BIOS Engineer to join our system engineering team. In this role, you will work closely with Systems Engineers to troubleshoot, validate, and optimize firmware and low-level software across a diverse portfolio of platforms built on AMD, Intel, and ARM-based CPUs, with a focus on DDR memory subsystems and other critical components. You will play a key role in bringing up/troubleshooting and validating memory subsystem/components on different platforms, resolving complex hardware-software interface issues, and ensuring robust interoperability/compatibility of subsystems/components and production readiness. Key Responsibilities * Analyze, troubleshoot, and customize BIOS/UEFI firmware for platforms using AMD EPYC/Ryzen, Intel Core/Xeon, and ARM-based processors. * Collaborate closely with Systems Engineers to troubleshoot and validate subsystems and components across the full platform stack. * Lead BIOS-level bring-up and validation for new hardware platforms, including debug of CPU, chipset, and memory (DDR5) subsystems. * Analyze and resolve hardware-firmware interface issues including POST failures, memory training errors, PCIe enumeration problems, and thermal/power sequencing anomalies. * Configure and validate DDR5 memory subsystems, including SPD/XMP programming, memory training tuning, RAS features, and JEDEC compliance. * Develop and execute validation test plans for BIOS features, power management (ACPI/S-states), security features (Secure Boot, TPM, AMD PSP, Intel TXT/SGX), and boot flows. * Work with CPU vendors to ensure the adoption of certain BIOS customization for certain platforms * Debug using industry-standard tools such as JTAG/ITP debuggers, logic analyzers, oscilloscopes, and serial console output. * Author and maintain issue logs/notes, validation reports, debug guides, and internal technical documentation. * Participate in design reviews, hardware bring-up planning, and cross-functional meetings * Support manufacturing and sustaining engineering with BIOS customization, factory programming, and field issue resolution. ## Related Videos - [Prototyping with Hardware and the Web](https://www.wearedevelopers.com/videos/651-prototyping-with-hardware-and-the-web) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [10M Data Records Lost, Underwater Computing, and Psychedelic Fish - Matthias Geniar](https://www.wearedevelopers.com/videos/1908-10m-data-records-lost-underwater-computing-and-psychedelic-fish-matthias-geniar) - [How a Small Team Shrank a Microsoft Monorepo by 94%](https://www.wearedevelopers.com/videos/1236-how-a-small-team-shrank-a-microsoft-monorepo-by-94) - [How to Submit CFPs and Get into Public Speaking - Moran Weber](https://www.wearedevelopers.com/videos/2112-how-to-submit-cfps-and-get-into-public-speaking-moran-weber) - [Project Fugu: Extending the web](https://www.wearedevelopers.com/videos/832-project-fugu-extending-the-web) ## Related Articles - [Dev Digest 129 - Now that's what I call private data!](https://www.wearedevelopers.com/magazine/468-dev-digest-129-now-that-s-what-i-call-private-data) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Dev Digest 138 - Are you secure about this?](https://www.wearedevelopers.com/magazine/486-dev-digest-138-are-you-secure-about-this) - [Dev Digest 182: GPT5 Prompts, MCP Vulnerabilities, Code Traps](https://www.wearedevelopers.com/magazine/622-dev-digest-182-gpt5-prompts-mcp-vulnerabilities-code-traps) - [Data Science & more: The Lopez dilemma](https://www.wearedevelopers.com/magazine/10-data-science-more-the-lopez-dilemma) - [Dev Digest 127 - putting 5 rings on it](https://www.wearedevelopers.com/magazine/464-dev-digest-127-putting-5-rings-on-it)