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# Chief Fpga & Soc Architect - Lógica Programable

- **Company:** Grupo Oesía
- **Location:** Rivas-Vaciamadrid, Spain
- **Contract:** Permanent contract
- **Skills:** Field-Programmable Gate Array (FPGA), SystemVerilog, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, ModelSim
- **Published:** August 11, 2026
- **Apply:** https://www.buscojobs.com.es/chief-fpga-soc-architect-logica-programable-en-rivas-vaciamadrid-ID-366941109

## About the Role

Se requieren ?10 años de experiencia, Ingeniería electrónica o telecomunicaciones y habilidades de liderazgo técnico.
Importante experiencia en verificación UVM, diseño RTL (VHDL/Verilog/SystemVerilog) y herramientas Vivado/ModelSim/LiberoSoC, con foco en DO-254 y

## Description

Grupo Oesía busca un/a Chief Engineer de Lógica Programable para liderar la definición técnica, el diseño y desarrollo de soluciones FPGA/SoC en proyectos del sector aeroespacial y defensa, ubicados en Madrid y en modalidad híbrida.Se requieren ?10 años de experiencia, Ingeniería electrónica o telecomunicaciones y habilidades de liderazgo técnico.Importante experiencia en verificación UVM, diseño RTL (VHDL/Verilog/SystemVerilog) y herramientas Vivado/ModelSim/LiberoSoC, con foco en DO-254 y#J-*****-Ljbffr


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