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# Principal FPGA Electric Engineer - IPT GPI

- **Company:** Northrop Grumman
- **Location:** Chandler, AZ, United States
- **Experience:** Experienced
- **Salary:** $98,400.0 - $146,600.0
- **Contract:** Permanent contract
- **Skills:** Configuration Management, Communications Protocols, Software Debugging, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Open Source Technology, PCI Express, Systems Development Life Cycle, Static Timing Analysis, System on a Chip, Universal Asynchronous Receiver/Transmitter, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, ModelSim, Hardware Testing, Hardware Debugging
- **Published:** May 19, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=589b3a50cd4bb1c9

## About the Role

* Bachelor's degree in Electrical Engineering or Physics from an accredited university and 5 years of related experience, or a Master's degree and 3 years of experience.
 * Security Clearance: U.S. citizenship; ability to obtain and maintain a DoD Secret clearance (active preferred).
 * FPGA/SoC Design: Proven experience in designing complex FPGA firmware using VHDL or Verilog.
 * FPGA/SoC Design: Experience with firmware development for Xilinx/AMD FPGAs & SoCs. Versal experience a plus.
 * FPGA/SoC Design: Experience with managing design constraints (timing, power, I/O) and performing static timing analysis to meet critical performance targets using Vivado or equivalent tools.
 * FPGA/SoC Design: Experience with developing complex firmware blocks in VHDL (preferred) or Verilog targeting various FPGA families
 * Experience with high-speed communication protocols (e.g. PCIe, Ethernet)
 * Verification: Proficiency in development, verification & debug of MOSA type interfaces/buses (UART, SDLC, Ethernet, PCIe, AXI4)
 * Verification: Proficiency with simulation tools (Questa/ModelSim) and hardware debugging tools (logic analyzers, oscilloscopes).
 * Verification: Proficiency in creating and executing verification plans using simulation, analysis, and hardware test.
 * Verification: Proficiency with Open Source VHDL Verification Methodology (OSVVM) or Universal Verification Methodology (UVM). OSVVM preferred

## Description

As a principal FPGA design engineer, you will work closely with senior FPGA engineers and cross-disciplinary teams to address design challenges and ensure successful integration of build onto hardware. Your role will primarily focus on developing and executing test benches, independent of the design group, to validate that FPGA designs meet functional and timing requirements while adhering to internal design standards. The selected candidate should thrive in a fast-paced work environment with significantly diverse assignments and collaborative/team settings across all levels., * Work closely with senior FPGA engineers or other engineering teams (e.g. hardware, algorithms, or software) to address design challenges

 * Develop and execute test benches to validate that the design meets functional and timing requirements
 * Compliance with standards, especially familiarizing with internal design standards
 * Ensure configuration management of possible multiple build configurations of FPGA bitstreams to support different use cases or platform requirements
 * Prepare design documentation, including design schematics, simulation results, and verification reports and present the to the team and leads
 * Continuous learning by staying updated with evolving FPGA technology, tools, and methodologies


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