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# Senior Digital Verification Engineer

- **Company:** Allegro MicroSystems
- **Location:** Musselburgh, UK
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Systems Engineering, C++ (Programming Language), Code Coverage, Software Debugging, Oracle Virtual Machine, Regression Testing, Specman, Subsystems, System on a Chip, SystemVerilog, Tcl (Programming Language), Verilog, Virtual Memory, Jama (Software), Caching
- **Published:** August 11, 2026
- **Apply:** https://find.jobs/jobs-near-me/apply/ats-redirect/?id=2919013306-2

## About the Role

Engineering or equivalent, Languages: System Verilog, Verilog, UVM/OVM, Specman, C/C++, ASM, TCL/TK, PythonKnowledge of the embedded SoC design and verification life-cycle with an emphasis on design verification tasks such as: test plan development, test bench creation, test coverage analysis and debug of unexpected design behaviour.Knowledge of CPU, Memory or I/O Subsystem microarchitectures (caches, virtual memory, DMA, memory access optimizations).Experience identifying functional coverage conditions based on microarchitecture specificationsExperience of SystemVerilog digital using UVM -SVExpertise building Mixed-Signal testbenches, checkers and tests.Expertise creating and using real-numbered analog behavioral models in SystemVerilog/Verilog-AMS or electrical behavioral models in Verilog-AExperience of script generation for processing results as well as regression control configurationExperience of constrained random verification.Experience of bus-functional model development for

## Description

microarchitecture specifications.Creating and maintaining SystemVerilog/UVM-based verification environments to achieve required coverage metrics.Defining and creating UVM-SV test environments, test plans, tests, and functional coverage.Analyzing test results, enhancing test coverage, and debugging unexpected design behavior.Running and maintaining regression test suites.Preparing and/or leading verification reviews.Collaborating with the System Engineering team on JAMA requirements.Identifying functional coverage conditions derived from microarchitecture specifications.Building mixed-signal testbenches, checkers, and tests.Implementing constrained random verification methodologies.Developing bus-functional models for verifying custom or industry-standard interfaces.Defining project deliverables and tasks, and tracking their on-time execution with a strong focus on quality.Who You AreThe successful candidate will possess at least a, Bachelors degree in Electrical and/or Electronic


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