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# STA Engineer

- **Company:** Propertyvalue
- **Location:** Barcelona, Spain
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Firmware, Python (Programming Language), PCI Express, Static Timing Analysis, Tcl (Programming Language), Scripting, Application Specific Integrated Circuits, Physical Design
- **Published:** August 11, 2026
- **Apply:** https://es.trabajo.org/oferta-4021-01f51a85db954de27eb70ead2faefdd2

## About the Role

reports and drive closure actions * Contribute to timing methodology improvements * Support tape out readiness from a timing perspective Requirements: * Senior level experience in static timing analysis * Strong experience with top level timing constraints * Strong knowledge of SDC and timing exceptions * Experience with clock and reset strategy * Experience supporting timing closure for SoC or complex ASIC designs * Familiarity with physical implementation flows * Strong scripting skills, Tcl, Python or Shell * Experience with EDA timing tools * English level C1 * Bachelor, Master or PhD in Electrical Engineering, Microelectronics, Computer Engineering or related field Preferred / Valued knowledge: * Experience working with RISC V architecture is highly valued, especially within processor, SoC, RTL, verification, firmware, software, PCIe, DDR, PCS, DFT, Physical Design or hardware environments. What's in it for you? Our client offers an exciting, challenging role in a



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