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# Performance Co-Design Engineer, Google Cloud TPU

- **Company:** Google LLC
- **Location:** Sunnyvale, TX, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Computer Engineering, Hardware Design, Systems Analysis, Machine Learning, Software Architecture, Google Cloud, AI Platforms, Information Technology, Hardware Acceleration, Machine Learning Operations
- **Published:** August 11, 2026
- **Apply:** https://us.experteer.com/career/view-jobs/performance-co-design-engineer-google-cloud-tpu-sunnyvale-tx-usa-58901917

## About the Role

researchers to transition innovations to production * Contribute to architectural roadmaps for AI serving and training capabilities using custom silicon Tasks * Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent practical experience * 10 years of experience in computer architecture, chip architecture, or hardware-software co-design * Experience developing systems for performance modeling, simulation, or system analysis Key requirements * bonus target * equity * benefits

## Description

Experteer Overview As a Staff Co-Design Engineer on the TPU Architecture team, you shape the roadmap for AI/ML hardware acceleration and drive innovations from research to production. You work across AI research, hardware design, and software architecture to optimize training and serving of large models. You develop cycle-accurate models and simulators to quantify microarchitectural choices and guide scalable, power-efficient accelerators. You'll influence TPUs and related infrastructure powering Google's AI platforms at scale. Compensation / Benefits * Define and optimize hardware/software stack for performant ML training and inference * Collaborate with research and modeling teams to scale model architectures while improving hardware efficiency * Develop configurable architectural simulators and cycle-accurate performance models * Perform system-level analysis of distributed ML systems balancing compute, memory, and inter-chip networks * Engage with hardware design, compiler, and ML researchers to transition innovations to production * Contribute to architectural roadmaps for AI serving and training capabilities using custom silicon Tasks * Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent practical experience * 10 years of experience in computer architecture, chip architecture, or hardware-software co-design * Experience developing systems for performance modeling, simulation, or system analysis Key requirements * bonus target * equity * benefits


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