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# Senior SoC Desgin & Integration Engineer

- **Company:** European Recruitment Alle Jobs anzeigen
- **Location:** Austria
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Integrated Development Environments, SystemVerilog, Verilog, Integration Frameworks, Code Inspection
- **Published:** August 12, 2026
- **Apply:** https://careerjet.at/jobad/ate389b5ed7d1f610e817ce9c4e9722238

## About the Role

* Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
 * 5+ years of digital design and SoC development experience.
 * Strong expertise in:

o RTL design using Verilog/SystemVerilog
o Logic synthesis
o CDC and Lint analysis
o Static verification debugging and closure

 * Minimum 2+ years of SoC/IP integration experience.
 * Experience with hierarchical design and integration decision-making.
 * Knowledge of interface standards and protocol integration.
 * Strong understanding of multi-processor SoC architectures and NoC/NIC concepts.
 * Experience working in multinational/global development teams.

Preferred Skills

 * Hands-on experience with Magillem (IP-XACT) for IP packaging, configuration, and integration.

 * Experience with:

o SpyGlass (CDC/Lint) or equivalent tools
o Cadence Genus/Synthesis tools

 * Knowledge of audio interfaces and standards such as:

o I2S
o SPDIF
o PDM
o TDM (preferred)
Desired Attributes

 * Strong analytical and debugging skills.
 * Excellent communication and collaboration abilities.
 * Ability to work independently in a fast-paced SoC development environment.
 * Proactive problem-solving mindset and ownership attitude.

## Description

* Design, develop, and integrate Audio IP blocks using Verilog/SystemVerilog.
 * Support IP delivery and up-integration into Atlas SoC architectures.
 * Perform RTL development, synthesis, and design optimization.
 * Execute and resolve static verification checks including:

o CDC (Clock Domain Crossing)
o Linting
o Structural design analysis

 * Review, analyze, and resolve SpyGlass/static verification waivers.
 * Drive hierarchical integration activities across multiple design levels.
 * Manage interface modifications and signal propagation through design hierarchies.
 * Identify and standardize common interfaces across IPs and subsystems.
 * Collaborate with international teams across multiple geographical locations.
 * Interface with complex multi-processor SoC architectures and Network-on-Chip (NoC/NIC) infrastructures.
 * Rapidly adapt to NXP design methodologies, processes, and quality standards.
 * Support IP configuration, packaging, and integration workflows using Magillem/IP-XACT methodologies.


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