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# Digital Design

- **Company:** NXP
- **Location:** Austin, TX, United States
- **Salary:** $119,025.0
- **Contract:** Internship / Graduate position
- **Skills:** Very-Large-Scale Integration, C++ (Programming Language), Computer Engineering, Digital Electronics, Logic Synthesis of Circuits, Microprocessors, Digital Technology, Python (Programming Language), Static Timing Analysis, SystemVerilog, Verilog, Programming Languages
- **Published:** August 13, 2026
- **Apply:** https://nxp.wd3.myworkdayjobs.com/careers/job/Austin-Oakhill-Office/Digital-Design_R-10066241

## About the Role

Master's degree in Electrical Engineering, Electronics Engineering, or Computer Engineering (with related variants such as VLSI or Physics), foreign equivalent or related field., Position requires knowledge gained via completion of a graduate-level course, thesis, internship or related occupation involving:

 1. Programming languages Python, C/C++;

 2. Verilog and System Verilog;

 3. UVM and Functional Verification;

 4. Computer Architecture,

 5. Synopsis Design Vision,

 6. RTL Design,

 7. Microprocessor System Design and Digital Systems Design, and

 8. Digital Integrated Circuit Design.

## Description

Duties: Perform semiconductor engineering design, development, and testing for firm products and devices in conjunction with product development for the electronic communications industry. Review IP microarchitecture features and interface specifications with microarchitect and/or senior engineers. Modify IP to replace coded hardware structures with standardized structures for clock-domain crossing (CDC), design-for-test (DFT), clocks and resets. Execute RTL-to-RTL logic equivalency checks (LEC) and perform design quality checks, including Lint, clock domain crossing (CDC) analysis, static timing analysis (STA). Reset domain crossing (RDC), and run NXP specific IP release tools to document correctness of IP release. Collaborate with verification team to develop test plans and complete verification execution to 100% coverage, and in developing improved methods of verification. Track metrics during IP development, include development plan milestones, code and functional coverage, defect
tickets. Deliver completed IP, including RTL design and quality signoff evidence.


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