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# Sr. ASIC Design Engineer, Cloud-Scale Machine...

- **Company:** Amazon.com, Inc.
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Salary:** $159,200.0 - $215,300.0
- **Contract:** Permanent contract
- **Skills:** Amazon Web Services, Very-Large-Scale Integration, Software Quality, Computer Engineering, Microarchitecture, Data Centers, Software Debugging, Python (Programming Language), Machine Learning, Azure Machine Learning, System on a Chip, SystemVerilog, Scripting, Application Specific Integrated Circuits
- **Published:** August 15, 2026
- **Apply:** https://www.juju.com/job/00000000gn7004

## About the Role

Are familiar with scripting in Python

 - Are proficient with assertions

 - Have good debug skills to analyze RTL test failures

 - Have a "Learn and Be Curious" mindset, B.S. in Electrical Engineering or related technical field

 - 5+ years in RTL design for SOC

 - 5+ years of VLSI engineering

 - 5+ years with code quality tools including: Spyglass, LINT, or CDC

Preferred Qualifications

 - Master's degree in electrical engineering, computer engineering, or equivalent

 - Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints

 - Experience with automation and scripting languages such as Python

 - Familiarity with data path design, interconnects, AXI protocol

 - Good analytical, problem solving, and communication skills

## Description

Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs., integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/DFT signal routing

 - As a key member of the ASIC design team, you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications.

 - Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements.

 - Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints.

 - Perform lint and clock domain crossing quality checks on the design.

 - Work with with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing and back-end teams to accomplish your tasks.


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