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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # SoC DFT Engineer, Cloud - **Company:** Google LLC - **Location:** Sunnyvale, CA, United States - **Experience:** Expert - **Salary:** $163,000.0 - $236,000.0 - **Contract:** Permanent contract - **Skills:** Bioinformatics, Cloud Computing, Databases, Computer Engineering, Software Debugging, Electronic Design Automation, Joint Test Action (IEEE Standards), Test Data, Strategies of Testing, System-level Testing, Information Technology - **Published:** August 16, 2026 - **Apply:** https://www.techcareers.com/job.asp?id=3355965877&tx=KR10201LFU&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54 ## About the Role Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area., * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. * 5 years of experience in DFT architecture, implementation, and verification for SoCs. * Experience in silicon bring-up, debug, or validation of DFT features. * Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT)., * Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. * 10 years of experience in DFT architecture, implementation, and verification for SoCs. * Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.). * Experience in DFT flow, including architecture, IP integration (e.g., Test controllers, TAP, MBIST), and interaction with synthesis and verification flows. * Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, TestKompress). * Knowledge of test standards (e.g., IEEE 1149.1, 1687) and test data Formats (e.g., BSDL, STIL). ## Description * Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG, and associated boot up and execution sequences. * Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality. * Develop diagnostic databases, software and hardware for logic and memory fail debug. * Design and implement system level test strategy. * Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT compression, Logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks. 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