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# Senior FPGA Engineer, LEO Payload FPGA

- **Company:** Amazon.com, Inc.
- **Location:** Los Angeles, CA, United States
- **Experience:** Expert
- **Salary:** $183,000.0 - $247,600.0
- **Contract:** Permanent contract
- **Skills:** Boolean Algebra, Data Transmissions, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Python (Programming Language), Network Service, Data Streaming, SystemVerilog, Application Specific Integrated Circuits, Software Verification
- **Published:** August 16, 2026
- **Apply:** https://www.juju.com/job/00000000gncxia

## About the Role

Bachelor's degree in Electrical Engineering or a related field

 - Experience with modern ASIC/FPGA design and verification tools

 - Experience in writing test scripts (Python preferred) to validate FPGA images in HW.

 - 7+ years experience in FPGA design and Implementation using System Verilog.

 - Experience with Xilinx/AMD (or Altera) FPGAs.

 - Experience with uArchitecture, RTL coding, FPGA optimization for timing & power, simulation, and validation

Preferred Qualifications

 - Experience developing python tests for both HW testing and Cocotb simulation enviroments.

 - Experience with high speed networking, SerDes, 50G/100G Ethernet or Interlaken.

 - Familiarity with AXI4 and AXI Streaming interfaces.

 - Proven track record of successfully fielding and supporting FPGA and ASIC products

## Description

Create FPGA solutions to support LEO's satellite communication system. This is a unique opportunity to define a new system with few legacy constraints. The FPGA design engineer will work with systems teams to define/develop/implement/test/release FPGA based solutions to enable LEO. This will focus on creating digital designs for networking functions using the latest generations of FPGA technologies and modern FPGA design processes and tools.

In this role you will:

Have ownership of one or more FPGA bitstreams. - Create and release FPGAs through the development phases of uArchitecture-RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon Validation

Collaborate with network communication system architects to define and design/implement/test/release/support networking functions targeted to FPGA technology

Collaborate with Digital Communications/Networking system architects and design engineers to implement digital logic functions in FPGAs.

Collaborate with system architects and design engineers to implement digital logic functions in FPGA prototypes to validate/tradeoff architecture & design alternatives

Collaborate with systems architects, HW engineering design teams & FW/SW design teams to bring up and test systems combining FPGA, firmware, RF, and Networking functions.

Drive trade-off analysis to benefit customer experience and optimization of target technology resources for cost/size/power/performance/features


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