> Markdown version of [/jobs/ext/2116785-rtl-design-engineer](https://www.wearedevelopers.com/jobs/ext/2116785-rtl-design-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # RTL Design Engineer - **Company:** Advanced Micro Devices, Inc. - **Location:** Rochester, NY, United States - **Salary:** $144,800.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Systems Engineering, Microarchitecture, Software Debugging, Logic Synthesis of Circuits, Firmware, Python (Programming Language), Subsystems, System on a Chip, SystemVerilog, Tcl (Programming Language), Verilog, Scripting, Physical Design - **Published:** August 19, 2026 - **Apply:** https://jobs.localjobnetwork.com/apply/add/88080579/1 ## About the Role You have a passion for digital design, mixed-signal integration, and silicon that works for the first time. You are a team player with excellent communication skills and experience collaborating with design, analog, firmware, and physical design teams. You have strong analytical and problem-solving skills, and you are ready to take ownership of hard problems., * RTL design in SystemVerilog, with ownership of blocks or subsystems through tape-out * Hands-on experience with timing constraints (SDC) development and timing closure on production silicon * Proficiency with synthesis, lint, and CDC/RDC tools and their integration into a design flow * Strong scripting skills in Python and TCL * Top-level SOC or chip-level integration ownership on a mixed-signal device * Integration and debug of analog behavioral models (Verilog-AMS, real-number/wreal modeling) in a digital simulation environment * Low-power design methodology and UPF-based power intent * Familiarity with standard control interfaces used in power management (IC, SPI, APB, SVID/PMBus) * Post-silicon bring-up and debug experience, including silicon-to-RTL correlation ## Description The focus of this role is to own the top-level RTL design and integration of AMD's mixed-signal power management IP, and to drive that design through timing closure and tape-out in partnership with our physical design and verification teams., Top-Level SOC Design * Own top-level RTL design and analog macro integration for mixed-signal power management IC * Partner with analog macro teams on block integration, including bring-up and debug of analog behavioral models in the digital simulation environment * Author micro-architecture specifications in partnership with Architecture and Firmware Physical Design, Timing & Design Quality * Act as primary interface between RTL design and the Physical Design / timing closure team * Create and review timing constraints (SDC), including analog macro boundaries and clock-domain crossings * Drive timing closure and ECO support through tape-out; manage area, power, and floorplan tradeoffs with PD * Own RTL signoff before each release to PD: lint, CDC/RDC, synthesis QoR, and connectivity checks Verification & Bring-Up * Partner with the verification team to define and review test plans and coverage goals * Validate analog behavioral models against analog design intent for functionality and timing, and drive discrepancies to resolution with the Analog team * Debug block- and system-level simulation failures to root cause * Support post-silicon bring-up and silicon-to-RTL correlation Collaboration * Work across Analog, Firmware, Systems Engineering, and Architecture teams * Mentor junior engineers and lead design reviews, AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. 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