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# Sr. Principal Software Engineer

- **Company:** Cadence Design Systems, Inc.
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Salary:** $196,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Software Debugging, Digital Electronics, Logic Synthesis of Circuits, Perl (Programming Language), Hardware Design, Python (Programming Language), Network Service, Software Engineering, SystemVerilog, Verilog, Physical Design, Software Coding
- **Published:** August 19, 2026
- **Apply:** https://www.juju.com/job/00000000gnrr8n

## About the Role

+ RTL Design & Verification

 + Strong background in Verilog/SystemVerilog RTL for digital hardware design and simulation

 + Hands-on coding and automation skills using SystemVerilog/Verilog, plus scripting with Perl and Python

 + Mastery of UVM and directed testbench IP verification, including test planning, coverage closure, debug, and working with verification teams to drive quality

 + Knowledge of network structures and method for communicating data across an SoC

 + Full-Flow Development & Integration

 + Proven experience developing complex reusable IPs from architecture through delivery

 + Strong experience with synthesis, lint, CDC/RDC, formal checks, timing closure, physical design, and signoff workflows

 + Ability to manage internal and third-party/services IP integrations, including requirements review, interface alignment, quality checks, and delivery tracking

 + Ability to debug complex hardware issues across RTL, verification, synthesis, timing, and integration environments

 + Strong documentation skills for architecture specs, design specs, integration guides, and verification collateral

 + DFT Architecture

 + Deep understanding of digital design architecture, including subsystem integration, DFT, interconnects, memory-mapped interfaces, reset/clock architecture, and low-power design considerations

 + Strong knowledge of DFT requirements for SoCs, including scan, MBIST, LBIST, POST, IST, IJTAG, test access architecture, and design-for-testability tradeoffs

 + Knowledge of DFT IP concepts, hardware, and test network communication

 + Project Ownership & Team Communication

 + Experience leading design reviews, architecture reviews, microarchitecture reviews, and implementation readiness reviews

 + Strong project execution and project management skills, including planning, dependency tracking, risk management, milestone ownership, and cross-functional coordination

 + Ability to mentor senior and junior engineers and provide technical leadership across teams

 + Good communication skills with a development team spread across multiple locations

 + Prior experience with large software development projects is highly recommended

Preferred Skills

 + Experience with ISO 26262 functional safety concepts, including safety mechanisms, diagnostic coverage, safety requirements, and ASIL-oriented design flows

 + Exposure to security-aware hardware design, including secure boot concepts, access control, lifecycle management, key handling, or secure debug

 + Experience with automotive, industrial, AI, or hyperscaler-class IP development

 + Familiarity with Cadence flows such as Xcelium, JasperGold, Genus, Innovus, Tempus, Modus, and related signoff/debug environments

 + Experience driving IP maturity through reusable methodology, quality metrics, and scalable infrastructure



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