> Markdown version of [/jobs/ext/216238-remote-rtl-design-engineer-for-ai-evaluation-program](https://www.wearedevelopers.com/jobs/ext/216238-remote-rtl-design-engineer-for-ai-evaluation-program). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Remote RTL Design Engineer for AI Evaluation Program - **Company:** Leidos, Inc. - **Location:** Washington, DC, United States (Remote available) - **Experience:** Expert - **Salary:** $87,100.0 - $157,450.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Systems Engineering, Software Debugging, Logic Synthesis of Circuits, Electronic Design Automation, Firmware, Formal Verification, Field-Programmable Gate Array (FPGA), PCI Express, Static Timing Analysis, SystemVerilog, Verilog, Application Specific Integrated Circuits, Large Language Models - **Published:** May 31, 2026 - **Apply:** https://www.careerjet.com/jobad/us63f4f57abd21e27fa40f2abc0ef73aa3 ## About the Role This position involves contributing to an AI evaluation program focused on advanced silicon and chip-design workflows. We are looking for senior digital chip design and verification engineers who can dedicate significant time over the next few months to support this initiative., Track 1: RTL Design Engineer * 3, 10 years of experience in digital RTL design * Strong proficiency in Verilog / SystemVerilog * Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols * Experience with ASIC design flows: lint, synthesis, timing analysis, CDC, DFT-aware design * Familiarity with common EDA tools for simulation, waveform debug, lint, CDC, synthesis, timing analysis * Familiarity with leveraging LLM-based tools to accelerate chip design, RTL development, debug, documentation, or verification workflows * Ability to write clear design documentation and communicate technical tradeoffs * Experience debugging RTL issues using simulation logs and waveform viewers * Strong collaboration skills across architecture, verification, and implementation teams Preferred * AMBA protocols (AXI, AHB, APB) * Background in one or more of: CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect, low-power design * Exposure to formal verification or SV/UVM-based design verification Track 2: Design Verification Engineer * 3, 10 years of experience in design verification * Strong proficiency in SystemVerilog and UVM * Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols * Experience developing reusable verification components and testbench infrastructure * Constrained-random verification, functional coverage, assertions (SVA), coverage closure * Familiarity with EDA tools for simulation, waveform debug, coverage analysis, formal verification, regression management * Familiarity with LLM-based tools to accelerate verification, debug, test generation, documentation, or coverage analysis * Ability to write clear verification plans, debug reports, and technical documentation Preferred * AMBA protocols (AXI, AHB, APB) * Background in one or more of: CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect, low-power verification * Reusable verification IP, scoreboards, reference models, coverage-driven regression flows ## Description The Electronic Warfare Division of Leidos is looking for a FPGA DSP Firmware Engineer to work with a multi-disciplined design team (electrical engineers, systems engineers, scienti… + 1 month ago ## Related Videos - [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine) - [The LLM Evolution: From Sequence Imitation to Verifiable Reasoning](https://www.wearedevelopers.com/videos/100343-the-llm-evolution-from-sequence-imitation-to-verifiable-reasoning) - [You don't need to write the code. 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