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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Hardware Technical Program Manager - **Company:** Efficient LLC - **Location:** San Jose, CA, United States - **Experience:** Expert - **Salary:** $200,000.0 - $240,000.0 - **Contract:** Permanent contract - **Skills:** Adobe InDesign, Artificial Intelligence, Confluence, JIRA, Bug Tracking Systems, Software Bug Management, Computer Engineering, Decision Support Systems, Microprocessors, Emulators, Firmware, Data Flow Control, Field-Programmable Gate Array (FPGA), Internet Protocol, Microsoft Project, Program Design Languages, Release Management, Cadence Virtuoso, System on a Chip, Linux Virtual Server, Smartsheet, Application Specific Integrated Circuits, Software Distribution, Information Technology, Physical Design, Programming Languages - **Published:** August 21, 2026 - **Apply:** https://www.careerbuilder.com/job-details/hardware-technical-program-manager-san-jose-ca--b5c89b14-e6e7-4dbd-9725-b8d9b18e4f70 ## About the Role * B.S. in Electrical/Computer Engineering, Computer Science, or equivalent; M.S. or MBA a plus. * 7+ years in semiconductor/hardware engineering or program management, including at least 2 full SoC/ASIC programs taken from concept through tapeout and silicon bring-up. * Working fluency in the chip design flow: RTL, functional verification and coverage closure, DFT, synthesis, PnR, STA, physical signoff (DRC/LVS/IR/EM), GDSII handoff, and post-silicon validation. * Demonstrated ability to build and defend a bottoms-up schedule with critical path analysis and dependency mapping. * Track record influencing without authority - earning the technical credibility to push senior engineers on commitments and dates. * Strong written and verbal communication; able to run a room of principal engineers and an exec review with equal effectiveness. * Hands-on with program tooling: Jira, Confluence, MS Project/Smartsheet, and familiarity with the Synopsys/Cadence/Siemens EDA ecosystem. Desired Qualifications & Experience Requirements * Prior hands-on engineering experience in design, DV, or physical design before moving to program management. * Experience on advanced or FinFET nodes (16/12/7nm or more advanced) and direct foundry engagement (TSMC preferred). * Familiarity with AI/ML accelerators, dataflow or novel compute architectures.. * Experience managing emulation/FPGA prototyping programs and pre-silicon software enablement timelines. * Exposure to package/board co-design programs (FC-BGA, WLCSP) and OSAT coordination. * Experience with EVK/reference board programs and customer/FAE enablement schedules. * Familiarity with quality and compliance frameworks relevant to the target market (automotive, industrial, or security certifications)., ASIC (Application Specific Integrated Circuit), Analysis Skills, Artificial Intelligence (AI), Artificial Intelligence (AI) Programming Languages, Atlassian JIRA, Automotive Industry, Ball Grid Array (BGA), Budgeting, Bug Tracking/Defect Management, Business Administration, Cadence, Compensation and Benefits, Computer Architecture, Computer Engineering, Computer Firmware, Computer Science, Cross-Functional, DFT (Design for Test), DRC Flows, Decision Support, Ecosystems, Electrical Engineering, Energy Efficiency, Engineering, FPGA, Functional Testing, IP (Internet Protocol), IR (Infrared), Internet of Things, LVS Flows, Logistics, Low Power, Machine Tool, Microprocessor, Microsoft Project, Presentation/Verbal Skills, Printed Circuit Board Design, Production Schedule, Project/Program Management, Prototyping Programming Languages, RTL Design, RTL Verification, Regulatory Compliance, Resource Management, Risk, Risk Management, Semiconductor Manufacturing, Semiconductors, Silicon Bringup, Software Distribution, Supply Chain, System-on-a-Chip (SoC), Target Marketing, Technical Delivery, Technical Leadership, Writing Skills undefined: Efficient Computer ## Description We are looking for a Hardware Technical Program Manager to own the program end-to-end - from architecture freeze through RTL, verification, physical implementation, tapeout, bring-up, and production release. You will be the operational center of the program: building and defending the schedule, driving the critical path, surfacing risk early, and making the tradeoff conversations happen before they become slips. You'll work daily with architecture, RTL design, DV/emulation, DFT, physical design, package, firmware, and the foundry/IP vendor ecosystem. Join our team and help us shape the future of computing at the edge and beyond!, Own the Program * Own the silicon schedule from architecture freeze through tapeout, bring-up, and production with the schedule informed by customer requirements and internal functional leads. * Drive the weekly execution cadence (program reviews, design reviews, tapeout readiness) and maintain a single source of truth for status, dependencies, and decisions. Drive Cross-Functional Execution * Coordinate handoffs across architecture, RTL, DV/emulation, DFT, physical design, IP, package, and software * Manage the dependency chains hardware programs live and die on: IP delivery, PDK/library releases, EDA versions, and emulation capacity. * Run the tapeout checklist and signoff matrix (timing, power, IR/EM, DRC/LVS, DFT coverage, ECO closure, GDS handoff), holding owners to closure criteria. * Work with supply chain/logistics for: IP acquisition, silicon arrival, ATE/loadboard readiness, lab scheduling, bug triage, and ECO/respin decision support. Manage Risk & Decisions * Surface risk early with mitigation options and schedule impact quantified - late IP, coverage shortfalls, convergence misses, foundry slot changes. * Facilitate PPA, schedule, and scope tradeoffs, and document what was decided, by whom, and why. Coordinate Externally & Report Up * Interface with foundry, OSAT, IP, and EDA partners on deliverables, technology file releases, mask slots, and escalations; support export control/ECCN compliance with legal and operations. * Deliver crisp executive reporting - where the program stands, what's at risk, what decision is needed and by when - across distributed teams and time zones. * Track resource allocation and NRE/mask/license/prototype budgets against program needs. ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Improving quality with Agentic AI with Rovo Dev and Xray](https://www.wearedevelopers.com/videos/2005-improving-quality-with-agentic-ai-with-rovo-dev-and-xray) - [Thinking Differently - How to Make Money from Cyber Attacks & Cheats](https://www.wearedevelopers.com/videos/745-thinking-differently-how-to-make-money-from-cyber-attacks-cheats) - [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Collaboration Quantified: Lessons from Open Source Developer Networks](https://www.wearedevelopers.com/videos/1422-collaboration-quantified-lessons-from-open-source-developer-networks) ## Related Articles - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Now is the time for industrialized software development](https://www.wearedevelopers.com/magazine/601-now-is-the-time-for-industrialized-software-development) - [Dev Digest 129 - Now that's what I call private data!](https://www.wearedevelopers.com/magazine/468-dev-digest-129-now-that-s-what-i-call-private-data)