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# FPGA Engineer (SystemVerilog)

- **Company:** Vivid Resourcing
- **Location:** Barcelona, Spain
- **Salary:** €83,000.0 - €165,000.0
- **Contract:** Permanent contract
- **Skills:** Field-Programmable Gate Array (FPGA), SystemVerilog, Verilog
- **Published:** August 21, 2026
- **Apply:** https://www.jobleads.com/es/job/ed0d96450406a11a8c485e805a29b3e29

## About the Role

The right candidate has deep FPGA experience, strong Verilog/SystemVerilog design skills, and a solid grasp of CDC, timing, and verification.




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