> Markdown version of [/jobs/ext/2202102-fpga-rtl-engineer](https://www.wearedevelopers.com/jobs/ext/2202102-fpga-rtl-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # FPGA/RTL engineer - **Company:** Cowboy Space Corp. - **Location:** San Carlos, CA, United States - **Experience:** Expert - **Salary:** $150,000.0 - $200,000.0 - **Contract:** Permanent contract - **Skills:** Board Bringup, C (Programming Language), Macintosh Computers, Automation of Tests, C++ (Programming Language), Protocol Stack, Computer Engineering, Modems, Computer Terminals, Software Debugging, Embedded Software, Ethernet, Fault Tolerance, Firmware, Formal Verification, Field-Programmable Gate Array (FPGA), Hardware Description Language, Hardware Design, Network Topologies, Python (Programming Language), Network Architecture, Regression Testing, Software Engineering, Systems Architecture, System on a Chip, SystemVerilog, Systems Integration, Tcl (Programming Language), Verilog, Vivado, Network Switches, Network Routing, Scripting, Software Verification, Fpga Hardware, ModelSim, Data Management, Data Pipelines, Hardware Debugging - **Published:** August 23, 2026 - **Apply:** https://www.careerbuilder.com/job-details/fpga-engineer-san-carlos-ca--81cc4529-0ac9-4f79-a188-e7f56c886c92 ## About the Role * Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field * 5+ years of experience in FPGA/HDL design, including architecture, verification, synthesis, and timing closure * Proficiency in SystemVerilog or Verilog for production FPGA development * Hands-on experience with Xilinx/AMD FPGA platforms (e.g., Zynq, Zynq UltraScale+) and toolchains (Vivado, Vitis) * Experience designing high-speed digital interfaces and DDR/DMA-based datapaths * Experience integrating FPGA logic with embedded software, including memory-mapped register interfaces and driver-level debugging * Experience developing FPGA platforms for multi-gigabit data pipelines, including integrating forward error correction and other stabilization techniques - optical communication or high-speed Ethernet experience strongly preferred * Hands-on hardware bring-up and lab debugging experience with oscilloscopes, logic analyzers, and embedded debug tools * Demonstrated ability to own open-ended design problems independently and carry them from architecture through hardware and on-orbit operation Preferred Qualifications * Master's degree in Electrical Engineering, Computer Engineering, or a related discipline * Experience in aerospace, defense, semiconductor, or other high-reliability development * Experience with free-space or fiber optical communication systems - optical communication terminals, coherent/direct-detection modems, or high-speed optical transceivers * Experience implementing Ethernet or other high-speed serial protocol layers (MAC/PCS/PMA) directly in FPGA fabric - a big plus * Understanding of network topology and architecture (routing, switching, protocol stacks) - a bonus * Familiarity with Versal ACAP architecture and Quartus toolflows * Experience with simulation and verification tools such as Questa/ModelSim, Xcelium, or Verilator, and with UVM or other structured verification methodologies * Proficiency with C/C++, Python, and TCL for bring-up, test automation, and tooling * Experience with hardware-in-the-loop testing and automated regression of FPGA designs * Familiarity with fault-tolerant design and radiation effects mitigation (SEU scrubbing, TMR, configuration memory integrity) for space applications * Experience thriving in fast-paced, high-ownership environments with rapid iteration cycles, Aerospace and Defense, Apple Macs, Avionics, Broadband, C Programming Language, C++ Programming Language, Cancer, Category Development, Communication Systems, Computer Engineering, Computer Firmware, Computer Terminals, Data Management, Datapath Design, Debugging Skills, Debugging Tools, Dental Insurance, Design Verification, Developmental Disabilities, Documentation Design, Double Data Rate SDRAM, Electrical Engineering, Electricity, Embedded Software, Embedded Systems, Ethernet, FPGA, FPGA Design, Fiber Optics, Genetics, Government, Hardware Architecture, Hardware Description Language, Hardware Design, Hardware Repair, High Reliability, High Throughput, IR (Infrared), Laboratory, Logic Analyzer, Media Access Control (MAC), Medical Conditions, Memory Hardware, Military, ModelSim, Modems, Network Architecture/Engineering, Network Routing, Network Switching, Network Topology, Optical Transceivers, Oscilloscope, Protocol Analysis, Protocol Stack, Python Programming/Scripting Language, Regression Testing, Regulations, Root Cause Analysis, SERDES, Semiconductors, Simulation, Software Engineering, State Laws and Regulations, System Architecture, SystemVerilog, Tcl-Tk, Team Lead/Manager, Test Automation, Test Tools, Timing Verification, Transceivers, United States Citizen, Verilog Hardware Description Language, Vision Plan, Wheel/Front-End Loader ## Description We're looking for an experienced FPGA/RTL engineer to help build our state-of-the-art optical communication system - the hard-real-time logic that connects optical communication terminals to embedded computers. You'll work closely with our optical communication team to design and own HDL for optical-link interfaces and high-speed data pipelines for in-orbit and ground communications. This is active development on a live flight program with near-term launch milestones: you'll join a small team, take full ownership of workstreams from day one, and see your designs fly. Responsibilities * Design, implement, and verify HDL/RTL in SystemVerilog/Verilog for the FPGA subsystems of our state-of-the-art optical communication system, from architecture through on-orbit operation * Partner directly with the optical communication team to design and implement FPGA logic for free-space optical communication links, including modem interfacing, framing/synchronization, and high-throughput data pipelines * Develop high-throughput communication pipelines for moving compute and optical-link data from orbit to the ground, including high-speed Ethernet (10/25/40/100GbE) MAC/PCS logic, SERDES/transceiver configuration, and link-layer framing within the FPGA fabric * Build memory-mapped register interfaces (AXI) between FPGA logic and onboard flight software, and define the hardware/software contract with flight software engineers * Own timing closure, synthesis, and implementation across Zynq UltraScale+ and Versal targets using Vivado and related toolchains * Develop testbenches and simulation environments to verify designs before hardware, and validate on the bench with logic analyzers, oscilloscopes, and protocol analyzers * Lead board bring-up and hardware integration for new payload avionics, working closely with electrical and embedded software engineers * Investigate anomalies spanning the optical-link-to-ground and software chain, perform root cause analysis, and drive fixes across hardware/firmware/software boundaries * Document designs and interfaces, and pair with teammates to spread ownership of the FPGA function across the team ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) ## Related Articles - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Dev Digest 134 - Where pixels sing?](https://www.wearedevelopers.com/magazine/477-dev-digest-134-where-pixels-sing) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [Data Science & more: The Lopez dilemma](https://www.wearedevelopers.com/magazine/10-data-science-more-the-lopez-dilemma) - [Dev Digest 129 - Now that's what I call private data!](https://www.wearedevelopers.com/magazine/468-dev-digest-129-now-that-s-what-i-call-private-data) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers)