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# FPGA Verification Engineer - UVM Architect

- **Company:** QuEST Defense
- **Location:** Boston, MA, United States (Remote available)
- **Experience:** Expert
- **Salary:** $150,000.0 - $180,000.0
- **Contract:** Permanent contract
- **Skills:** Communications Protocols, Software Debugging, Field-Programmable Gate Array (FPGA), Hardware Interface Design, Python (Programming Language), Requirements Traceability, SystemVerilog, Scripting, Application Specific Integrated Circuits
- **Published:** May 16, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=44196e6b3008324b

## About the Role

* 8-12+ years of experience in FPGA or ASIC verification
 * Strong hands-on experience with SystemVerilog and UVM
 * Experience building UVM testbenches and reusable verification environments
 * Background in simulation, debugging, and coverage-driven verification
 * Experience with tools like QuestaSim, VCS, or similar
 * Understanding of hardware interfaces and RTL design
 * Ability to lead technical efforts and guide other engineers
 * Experience building UVM verification environments (SystemVerilog), including agents, drivers, monitors, and scoreboards
 * Ability to create self-checking simulations using predictors and coverage-based testing
 * Basic understanding of register modeling (UVM RAL) and how to test and validate register behavior in simulation
 * Experience with DO-254 or other safety-critical standards

Nice to Have

 * Experience with emulation tools (Siemens Veloce, Palladium, etc.)
 * Knowledge of high-speed interfaces or communication protocols
 * Experience with requirements tools (DOORS) or traceability
 * Exposure to aerospace, defense, or regulated industries
 * Experience with Python or automation scripting

## Description

* Lead development of SystemVerilog / UVM verification environments for FPGA designs
 * Build and improve testbenches, agents, scoreboards, monitors, and sequences
 * Define verification strategy, test plans, and coverage goals
 * Drive functional, code, and assertion coverage closure
 * Support both simulation and emulation workflows (Veloce or similar)
 * Review and improve existing verification environments and processes
 * Guide engineers on UVM best practices and debug complex issues
 * Support DO-254 verification activities (requirements traceability, test evidence, audits)
 * Work closely with design, systems, and program teams


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